The SDSP Read |
PROCEDURE memory_read (addr : IN bit_32; fetch_cycle : IN BOOLEAN; result : OUT bit_32) IS BEGIN | |
a_bus <= addr AFTER Tpd; --start bus cycle fetch <= bool_to_bit(fetch_cycle) AFTER Tpd; WAIT UNTIL phi1 = '1'; | Place address on a_bus |
IF reset = '1' THEN RETURN; END IF; read <= '1' after Tpd; -- T1 phase WAIT UNTIL phi1 = '1'; IF reset = '1' then RETURN; END IF; | Assert read signal |
LOOP -- T2 phase WAIT UNTIL phi2 = '0'; -- end of T2 IF reset = '1' then RETURN; END IF; IF ready = '1' then result := d_bus; EXIT; END IF; END LOOP; WAIT UNTIL phi1 = '1'; IF reset = '1' THEN RETURN; END IF; | |
read <= '0' AFTER Tpd; -- Ti phase at end of cycle END memory_read; |