USE WORK.SDSP_types.ALL;
ENTITY SDSP IS
GENERIC (Tpd : Time
:= unit_delay);
PORT ( d_bus : inout
bus_bit_32 bus;
a_bus : out bit_32;
read, write : out bit;
fetch : out bit;
ready : in bit;
phi1, phi2 : in bit;
reset:in bit);
END SDSP; USE WORK.SDSP_types.ALL;
ARCHITECTURE behavior OF SDSP IS
SUBTYPE reg_addr is NATURAL RANGE 0 to 255;
TYPE reg_array IS array (reg_addr) OF bit_32;
BEGIN
PROCESS
VARIABLE reg : reg_array;
VARIABLE PC : bit_32;
VARIABLE current_instr : bit_32;
VARIABLE op: bit_8;
VARIABLE r3, r1, r2 : reg_addr;
VARIABLE i8 : integer;
ALIAS cm_i : BIT IS current_instr(19);
ALIAS cm_V : BIT IS current_instr(18);
ALIAS cm_N : BIT IS current_instr(17);
ALIAS cm_Z : BIT IS current_instr(16);
VARIABLE cc_V, cc_N, cc_Z : bit;
VARIABLE temp_V, temp_N, temp_Z : bit;
VARIABLE displacement : bit_32;
VARIABLE effective_addr : bit_32; | |