The SDSP Read Memory Procedure-- Notes Page -- |
The memory read and write procedures exactly implement the timing
requirements presented several slides back. Since asynchronous events
cannot be modeled as such in VHDL processes or procedures, we emulate
an asynchronous reset by checking for it after each micro-operation.
It is instructive to examine the flow of execution here with the
timing model diagram to observe how direct the behavior mapping can be.