Testbench Body |
BEGIN cg : clock_gen PORT MAP (phi1 => phi, phi2 => phi2, reset => reset); proc : SDSP PORT MAP (d_bus => d_bus, a_bus => a_bus, read => read, write => write, fetch => fetch, ready => ready, phi1 => phi1, phi2 => phi2, reset => reset); mem : memory PORT MAP (d_bus => d_bus, a_bus => a_bus, read => read, write => write, ready => ready); END structure; |