The SDSP Testbench |
USE WORK.SDSP_types.ALL; ENTITY SDSP_test IS END SDSP_test; ARCHITECTURE structure OF SDSP_test IS COMPONENT clock_gen PORT (phi1, phi2 : OUT BIT; reset : OUT BIT); END COMPONENT; COMPONENT SDSP PORT (d_bus : INOUT bus_bit_32 bus; a_bus : OUT bit_32; read, write : OUT BIT; fetch : OUT BIT; ready : IN BIT; phi1, phi2 : IN BIT; reset : IN BIT); END COMPONENT; COMPONENT memory PORT (d_bus : INOUT bus_bit_32 bus; a_bus : IN BIT_32; read, write : IN BIT; ready : OUT BIT); END COMPONENT; | |
SIGNAL d_bus : bus_bit_32 bus; SIGNAL a_bus : bit_32; SIGNAL read, write : BIT; SIGNAL fetch : BIT; SIGNAL ready : BIT; SIGNAL phi1, phi2 : BIT ; SIGNAL reset : BIT; |