The incoming address bus splits into two parts, with lines A19-A14 being used to select the module.A13 and A12 are input to the chip enable logic, which is detailed in Fig.10-9(a).The chip enable logic has four outputs, \CE0 through \CE3, only one of which may be active at any one time.

\MWTC and the module select line are input to a write pulse generator which is constructed from two monostable multivibrators and is detailed in Fig.10-9(b).The output of this circuit is connected to the Write Enable (\WE) pins of all the memory devices and causes the data on D7-D0 to be put into the address byte.