Figure 10-7(a) illustrates the timing of a memory read cycle.The address is applied at point A, which is the begining of the read cycle and must be held stable during the entire cycle.In order to reduce the access time, the chip enable input should be applied before point B.The data output becomes valid after point C and remains valid as long as the address and chip enable inputs hold.

A typical write cycle is shown in Fig.10-7(b).In addition to the address and chip enable inputs, an active low write pulse on the R/W line and the data to be stored must be applied during the write cycle.