Bit 5 of the mode register specifies whether the contents of the address register are to be insremented (0) or decremented (1) after each transfer, thus determining the order in which the data are stored in memory.

If bit 4 is 1, then automatization is enabled.When the current address and current byte count registers are initially loaded their contents are also put in the base address and base byte count registers.If automatization is enabled, then the current registers are automatically reloaded from the base registers whenever the count goes to zero.

Bits 2 and 3 indicate the type of transfer to be made.There are three types: verify (00), write (01) and read (10).The verify type is for verifying information concerning the previous input or output operation and is not actually associated with a current transfer.It is of little interest to us and will not be discussed further.

The two LSBs of an output to a mode register direct the output to the indicated channel, i.e., select the mode register that is to receive the output.

In addition to block transfers between I/O or mass storage devices and memory, the 8237 can supervise memory-to-memory transfers.Such transfers are conducted by bringing bytes from the source memory area into 8-bit temporary register in the 8237 and then outputting them to the destination memory area.

Therefore, two bus cycles are required for each memory-to-memory transfer. The channel 0 current address register is used for source addressing. The channel 1 current address and current byte count registers provide the destination addressing and counting.