With regards to the control register, a memory-to-memory transfer is enabled by setting bit 0 to 1, in which case bit 1 = 1 indicates that the source address is to be held constant.

Bit 2 is used for enabling (0) or disabling (1) the controller and bit 3 specifies the type of timing.If the speed characteristics of the system permit, then bit 3 can be set to 1 to indicate compressed timing.With compressed timing only two clock cycles are needed to perform most transfers.

Bit 4 determines whether the priority is fixed or rotating.Normally, channel 0 has the highest priority and channel 3 the lowest;however, if bit 4 is 1, the priority will rotate after each transfer, e.g. , if the priority before a transfer is 2-3-0-1, then after the transfer it will be 3-0-1-2.By rotating the priority the controller can prevent one channel from dominating the bus.

A 1 in bit 5 indicates that these signals are to be extended over two clock cycles.The program can also specify whether the DREQ and DACK pins are to be active high or active low by setting or clearing bits 6 (DREQ) and 7 (DACK), respectively.

Bit 6 = 1 indicates that DREQ is active low and bit 7 = 1 indicates that DACK is active high.How these bits should be set depends on the characteristics of the associated interfaces.

The format of the status register is such that the lower 4 bits indicate the states of the terminal counts of the four channels and the upper 4 bits show the current presence of absence of DMA request.For the lower 4 bits a 1 in bit n indicates that the terminal count for channel n is active and for the upper four bits a 1 in bit n + 4 signals the presence of a request on channel n.


Each channel also has associated with it a request flag and a mask flag. A DMA request can be programmed as well as input through the DREQ pin.

The request and mask flags are programmed using commands in which bit 2 determines the setting of the flag and bits 1 and 0 give the channel number of the flag.The remaining bits are unused.

Besides the commands for setting the flags, there are a master clear command and a clear first/last flip/flop command.A master clear command has the same effect as a RESET signal.

The addressing of the various registers and commands associated with the controller is done via the \CS,\IOR,\IOW and A3-A0 lines.\CS=0 of course indicates that the controller is being accessed.

Addressing the control and status registers and giving commands are 
summarized as follows: 
                        __  __  __  __  ___  ___
                        A3  A2  A1  A0  IOR  IOW      Transfer or Command
                         
                         1   0   0   0   0    1      Read from status register                
                         1   0   0   0   1    0      Write to control register                
                         1   0   0   1   1    0      Write to a request flag
                         1   0   1   0   1    0      Write to a mask flag
                         1   0   1   1   1    0      Write to mode register
                         1   1   0   0   1    0      Clear first/last flip-flop
                         1   1   0   1   0    1      Read temporary register
                         1   1   0   1   1    0      Master clear
                         1   1   1   0   1    0      Clear mask flags
                         1   1   1   1   1    0      Write to all mask flags