Because these signals do not match the \RD,\WR and IO/ \M signals output by a minimum mode-8088, a read/write encoding circuit such as the one shown in Fig.9-39 is needed to perform the translation between the two sets of signals.
An 8237 includes control, status and temporary registers and four channels,each containing a mode register, current address register, base address register, current byte count register, base byte count register, request flag, and mask flag.
Each channel may be put in one of four modes, with its current mode being determinated by bits 7 and 6 of the channel's mode register.The four possible modes are:
Single Transfer Mode(01) - After each transfer the controller will release the bus to the processor for at least one bus cycle, but will immediately begin testing for DREQ inputs and proceed to steal another cycle as soon as a DREQ line becomes active.
Block Transfer Mode(10) - DREQ need only be active until DACK becomes active, after which the bus is not released until the entire block of data has been transferred.
Demand Transfer Mode(00) - This mode is similar to the block mode except that DREQ is tested after each transfer.If DREQ is inactive, transfers are suspended until DREQ once again becomes active, at which time the block transfer continues from the point at which it was suspended.This allows the interface to stop the transfer in the event that its device cannot keep up.
Cascade Mode(11) - In this mode 8237s may be cascaded so that more than four channels can be included in the DMA subsystem.In cascading the controllers, those in the second level are connected to those in the first level by joining HRQ to DREQ and HLDA to DACK.To converse space, this mode will not be considered further.
In all cases the count going to zero will cause \EOP to become active and the transfer process to cease.