PACKAGE my_stuff IS COMPONENT and_gate PORT (in1, in2 : IN BIT; out1 : OUT BIT); END COMPONENT; END PACKAGE my_stuff;
USE Work.my_stuff.ALL; ARCHITECTURE test OF test_entity IS SIGNAL S1, S2, S3 : BIT; BEGIN Gate1 : and_gate PORT MAP (S1, S2, S3); END test;