Instantiation Statements

ARCHITECTURE test OF test_entity IS
    COMPONENT and_gate
      PORT (in1, in2 : IN BIT;
               out1 : OUT BIT);
    END COMPONENT;
      SIGNAL S1, S2, S3 : BIT;
BEGIN
    Gate1 : and_gate PORT MAP (in1 => S1,
       in2 => S2, out1 => S3);
END test;