8-13 INTERRUPT PRIORITY MANAGEMENT
The interrupt priority management logic indicated in
Fig.8-1 can be implemented in several ways. It does
not need to be present in systems which use software
prority management or simple daisy chaining, but more
complex systems may require the efficiency gained by
including hardware for managing the I/O interrupts.
8-3-1 Interrupt System Based on a Single 8259A
The 8259A is contained in a 28-pin dual-in-line package
that requires only a +5V supply voltage. Its organization
is shown in Fig.8-17 along with its connections to a
maximum mode system. Its pins (other than the supply
voltage and ground pins) are defined as follows:
- D7-D0- For communicating with the CPU over the
data bus. On a few systems bus drivers may be needed, but on other
systems direct connections can be used.
- INT- To send interrupt request signals to the
CPU.
- /INTA- To receive interrupt acknowledge signals
from the CPU. The 8259A assumes that an acknowledgment
consists of two negative pulses, thus making it
compatible with 8086/8088 systems.
- /RD- To signal the 8259A that it is to place
the contents of the IMR, ISR, or IRR register or a
priority level on the data bus. Which of these possibilities
is placed on the bus depends on the state of the 8259A and
is discussed below.
- /WR- To signal the 8259A that it is ti
accept data from the data bus and use the data to set
the bits in the command words. How the received data are
distributed is discussed later.
- /CS- For indicating that the 8259A is being
accessed. This pin is connected to the address bus
through the decoder logic that compares the high-order
bits of the address of the 8259A with the address currently
on the address bus. Input to this pin can be combined
with /S2 to give the ready signal.
- A0- For indicating which port of the 8259A is
being accessed. Two address must be reserved in the I/O
address space for each 8259A in the system.
- IR7-IR0- For receiving interrupt requests from
I/O interfaces or other 8259As referred to as slaves.
- CAS2-CAS0- To identify a particular slave
device. Their function is considered in Sec.8-3-2.
- /SP / /EN- For one of two purposes: either
as an input to determine whether the 8259A is to be a
master (/SP / /EN =1), or as an output to disable the
data bus transceivers when data are being transferred
from the 8259A to the CPU. Whether the /SP / /EN pin is
used as an input or output depends on the buffer mode
discussed below.