8-1-1 Maximum Mode

A processor is in maximum mode when its MN / /MX pin is grounded. The maximum mode definitions of pins 24 through 31 are given in Fig.8-8 and a typical maximum mode configuration is shown in Fig.8-9. It is clear from Fig.8-9 that the main difference between minimum and maximum mode configurations is the need for additional circuitry to translatethe control signals. The circuitry is for converting the status bits /S0, /S1 and /S2 into the I/O and memory transfer signals needed to direct data transfers and for controlling the 8282 latches and 8286 transceivers. It is normally implemented with an Intel 8288 bus controller. Also included in the system is an interrupt priority management device: however, its presence is optional.

Figure 8-8 Maximum mode pin definitions
Pin(s)	Symbol	In/Out(3 State)	Description
24,25	QS1, QS0	O	Reflects the status of the instruction queue. This status indicates the activity in the queue during the previous clock cycle - see Chap. 11.
26, 27, 28	/S0, /S1, /S2	O-3	Indicates the type of transfer to take place during the current bus cycle: /S2 /S1 /S0 0 0 0 Interrupt acknowledge 0 0 1 Read I/O port 0 1 0 Write I/O port 0 1 1 Halt 1 0 0 Instruction fetch 1 0 1 Read memory 1 1 0 Write memory 1 1 1 Inactive - passive (1 represents high and 0 represents low.) The status becomes active prior to the beginning of a bus cycle and returns to inactive during the later part of the cycle.
29	/LOCK	O-3	Indicates the bus is not to be relinquished to other potential bus masters. It is initiated by a LOCK instruction prefix and is maintained until the end of the next instruction - see Chap.11. It is also active during and between the two /INTA pulses.
30	/RQ / /GT1	I/O	For inputting bus requests and outputting bus grants.
31	/RQ / /GT0	I/O	Same as /RQ / /GT1 except that a request on /RQ / /GT0 has higher priority.

Note: In maximum mode the 8086 and 8088 pins have the same definitions except for pin 34, which on the 8088 is always 1.

The HOLD and HLDA pins become the /RQ / /GT0 and /RQ / /GT1 pins. Both bus requests and bus grants can be given through each of these pins. They are exactly the same except that if requests are seen on both pins at the same time, then one on /RQ / /GT0 is given higher priority. A request consists of a negative puls arriving before the start of the current bus cycle. The grant is negative puls that is issued at the beginning of the current bus cycle provided that:

1. The previous bus transfer was not the low byte of a word to or from an odd address if the CPU is an 8086. For 8088, regardless of the address alignment the grant signal will not be sent until second byte of a word reference is accessed.
2. The first pulse of an interrupt acknowledgement did not occure during the previous bus cycle.
3. An instruction with a LOCK prefix is not being executed.