6-4 BLOCK TRANSFERS AND DMA

The activity involved in transferring a byte or word over the system bus is called a bus cycle. The execution of an instruction may require more than one bus cycle. For example the instruction: 

 MOV AL, TOTAL
would use a bus cycle to bring in the contents of TOTAL in addition to the cycle needed to fetch the instruction.
During any given bus cycle one of the system components connected to the system bus is given control of the bus. This component is said to be the master during that cycle and the component it is communicating with is said to be the slave.

The 8086 receives bus requests through its HOLD pin and issues grants from its hold acknowledge (HLDA) pin. A request is made when a potential master sends a 1 to the HOLD pin. Normally, after the current bus cycle is complete the 8086 will respond by putting a 1 on the HLDA pin. When the requesting device receives this grant signal it becomes the master. It will remain master until it drops the signal to the HOLD pin, at which time the 8086 will drop the grant on the HLDA pin.

A block transfer is a succession of the datum transfers described above. Each successive DMA uses the next consecutive memory location.

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