A more flexible hardware/software priority arrangement can be had by designing a programmable interrupt priority management circuit and including it in the bus control logic. Typical, such a circuit would be designed and inserted in the system as shown in Fig.6-15. The INTR and /INTA pins would not be connected to the interface but would be connected only to the management circuit.

Many microprocessor manufacturers produce interrupt priority management IC devices to supplement their CPU devices. The Intel 8259A programmable interrupt controller is designed to work with the 8086 and 8088 CPUs. It is similar to the management circuit shown in Fig.6-15, but has many features not considered above.