6-3 INTERRUPT I/O

Even though programmed I/O is conceptually simple, it can waste a considerable amount of time while waiting for ready bits to become active. In the above example, if the person typing on the terminal could type 10 characters per second and only 10 µs is required for the computer to input each character, then approximately

of the time is not being utilized.

As was seen in Sec.4-4 an interrupt is an event that causes the CPU to initiate a fixed sequence, known as an interrupt sequence. Before an 8086 interrupt sequence can begin, the currently executing instruction must be completed unless the current instruction is a HLT or WAIT instruction. For a prefixed instruction, because the prefix is considered as part of the instruction, the interrupt request is not recognized between the prefix and the instruction. In the case of the REP instruction, the interrupt request is recognized after the primitive operation following the REP is completed, and the return address is the location of the REP prefix. For MOV and POP instructions in which the destination is a segment register, an interrupt request is not recognized until after the instruction following the MOV or POP instruction is executed.
For the 8086, once the interrupt request has been recognized, the interrupt sequence consists of:

  1. Establishing a type N.
  2. Pushing the current contents of the PSW, CS and IP onto the stack (in that order).
  3. Clearing the IF and TF flags.
  4. Putting the contents of the memory location 4*N into the IP and the contents of 4*N+2 into the CS.
Thus, an interrupt causes the normal program sequence to be suspended and a branch to be made to the location indicated by the double word beginning at four times the type (i.e. the interrupt pointer). Control can be returned to the point at which the interrupt occurred by placing an IRET instruction at the end of the interrupt routine.

It was mentioned that there are two classes of interrupts, internal and external interrupts, with external interrupts being caused by a signal being sent to the CPU through one of its pins, which for the 8086 is either the NMI pin or the INTR pin. An interrupt initiated by a signal on the NMI pin is called a nonmaskable interrupt and will cause a type 2 interrupt regardless of the setting of the IF flag. Nonmaskable interrupt signals are normally caused by circuits for detecting catastrophic events.

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