To avoid this problem, the processor that starts executing its XCHG instruction
first (which in this example is processor A) must have exclusive use of the bus
until the XCHG instruction is completed.On the 8086/8088 this exclusive use is
guaranteed by a LOCK prefix:
which for a maximum mode CPU, activates the \LOCK output pin during the execution
of the instruction that follows the prefix.
The \LOCK signal indicates to the bus control logic that no other processors may
gain control of the system bus until the locked instruction is completed.To get
around the problem encountered in the above example the XCHG instructions could
be replaced with:
TRYAGAIN: LOCK XCHG SEMAPHORE,AL
This would ensure that each exchange will be completed in two consecutive
bus cycles.
Physically, in a loosely coupled system each processing module includes a bus
arbiter and the bus arbiters are connected together by special control lines
in the system bus.One of these lines is a busy line which is active whenever
the bus is in use.
If a \LOCK signal is sent to the arbiter controlling the bus, then that arbiter
will retain control of the system by holding the busy line active until the
\LOCK signal is dropped.Thus, if a processor applies a \LOCK signal throughout
the execution of an entire instruction, its arbiter will not relinquish the
system bus until the instruction is complete.
Another possible application of the bus lock capability is to allow fast
execution of an instructionwhich requires several bus cycles.
For example, in a multiprocessor system a block of data can be transferred at
a higher speed by using the LOCK prefix as follows:
LOCK REP MOVS DEST,SRC
During the execution of this instruction the system bus will be reserved for
the sole use of the processor executing the instruction.