11-1 QUEUE STATUS AND THE LOCK FACILITY

Although the maximum mode and the 8288 bus controller were introduced in Chap. 8, their multiprocessing features were not consideredat that point.

Because the 8086 has a 6-byte instruction queue and the 8088 has a 4-byte queue, the instruction that has just been fetched may not be executed immediately.In order to allow external logic to monitor the execution sequence, a maximum mode 8086/8088 outputs the queue status through its QS1 and QS0 pins.During each clock cycle the queue status is examined and the QS1 and QS0 bits are encoded as follows: 

      00 - No instruction was taken from the queue. 
      01 - The first byte of the current instruction was taken from the queue.
      10 - The queue was flushed because of a transfer instruction.
      11 - A byte other than the first byte of an instruction was taken from the queue.

Normally, semaphores are used to ensure that at any given time only one process may enter its critical section of code in which a shared resource is accessed.Let us now reconsider the semaphore implementation. 
                 MOV    AL,0
    TRYAGAIN:    XCHG   SEMAPHORE,AL
                 TEST   AL,AL
                 JZ     TRYAGAIN
                  .  }  Critical section in which a process 
                  .  }  accesses a shared resource 
                  .  } 
                 MOV    SEMAPHORE,1
This implementation works fine for a system in which all of the processes are executed by the same processor, because the processor cannot switch from one process to another in the middle of an instruction.

Suppose that processor A is concurrently ready to update a record in memory while processor B is ready to sort the same record.Since the both processors are running independently, they might test the semaphore at the same time.

Note that the XCHG instruction requires two bus cycles, one which inputs the old semaphore and one which outputs the new semaphore.It is possible that after processor A fetches the semaphore, processor B gains control of the next bus cycle and fetches the same semaphore.
Suppose that the location SEMAPHORE contains a 1 and both processors A and B are executing 
                       TRYAGAIN:    XCHG    SEMAPHORE,AL
and
  1. Processor A uses the first available bus cycle to get the contents of SEMAPHORE.
  2. Processor B uses the next bus cycle to get the contents of SEMAPHORE.
  3. Processor A clears SEMAPHORE during the next bus cycle, thus completing its XCHG instruction.
  4. Processor B clears SEMAPHORE during the next bus cycle, thus completing its XCHG instruction.
After this sequence is through, the AL registers in both processors will contain 1 and the 
                                    TEST    AL,AL
instruction will cause the JZ instructions to fail.Therefore, both processors will enter their critical sections of code.

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