9-3-1 Intel's 8254 Programmable Interval Timer


The registers can be accessed according to the following table: 

      __   __   __   
      CS   RD   WR   A1   A0          Transfer
      
      0    1    0    0    0        To counter 0 CR
      0    1    0    0    1        To counter 1 CR
      0    1    0    1    0        To counter 2 CR
      0    1    0    1    1        To a control register or indicates a command
      0    0    1    0    0        From counter 0 OL or status register  
      0    0    1    0    1        From counter 1 OL or status register
      0    0    1    1    0        From counter 2 OL or status register
All other combinations result in the data pins being put into their high-impedance state.When A1=A0=1, whether a control register is being written or a command is being given depends on the MSBs of the byte being output.

There are two types of commands, the counter latch command, which causes the CE in the counter specified by the two MSBs of the command to be latched into the corresponding OL, and the read back command, which may cause a combination of the CEs to be latched or "prepare" a combination of status registers to be read.

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