System Level VHDL Constructs
For all examples in this section, assume the existence of a multi-values logic package ATT_MVL type MVL is 'U', '0', '1', 'Z');
type
MVL_VECTOR is
array
(NATURAL
range
<>) of MVL;
overloaded
logical operators
for both MVL and MVL_VECTOR
overloaded
"+" and "-"
arithmetic operators on MVL_VECTOR
integer-to-MVL_VECTOR conversion functions (int2MVL, MVL2int)
