Synthesizing OO-VHDL

The high-level abstractions used in OO-VHDL models do not allow them to be synthesized directly. For example, a synthesis tool cannot (and should not) conjure an implementation for the abstract communication mechanism used by OO-VHDL components. However, by means of transformation tools directed or specified by the user, the descriptions of OO-VHDL models can be translated into synthesizable VHDL code so that an implementation is generated through a user-directed synthesis process.