USE WORK.SDSP_types.ALL;
ENTITY clock_gen IS
GENERIC (Tpw : TIME; -- clock pulse width
Tps : TIME); -- pulse separation between phases
PORT (phi1, phi2 : OUT BIT;
reset : OUT BIT);
END clock_gen;
ARCHITECTURE behavior OF clock_gen IS
CONSTANT clock_period : TIME := 2*(Tpw+Tps);
BEGIN
reset_driver : reset <= '1', '0' AFTER 2*clock_period+Tpw;
clock_driver : PROCESS
BEGIN
phi1 <= '1', '0' AFTER Tpw;
phi2 <= '1', '0' AFTER Tpw+Tps, '0' after Tpw+Tps+Tpw;
WAIT FOR clock_period;
END PROCESS clock_driver;
END behavior; |