VHDL uses bus resolution functions to resolve the final value of multiple signal assignments
FUNCTION wired_and (drivers : MVL_VECTOR) RETURN MVL IS
VARIABLE accumulate : MVL := '1';
BEGIN
FOR i IN drivers'RANGE LOOP
accumulate := accumulate AND drivers(i);
END LOOP;
RETURN accumulate;
End wired_end;
Bus resolution functions may be user defined or called from a package