A Design Example - |
ENTITY count2 IS
GENERIC (prop_delay : TIME := 10ns);
PORT (clock : IN BIT;
q1, q0: OUT BIT);
END count2;
ARCHITECTURE behavior OF count2 IS
BEGIN
count_up: PROCESS (clock)
VARIABLE count_value: NATURAL := 0;
BEGIN
IF clock='1' THEN
count_value := (count_value+1) MOD 4;
q0 <= bit'val(count_value MOD 2) AFTER prop_delay;
q1 <= bit'val(count_value/2) AFTER prop_delay;
END IF;
END PROCESS count_up;
END behavior; |