Using VHDL, a system designer can model a circuit (i.e., a component
or system) at multiple levels of abstraction. In prior lessons, we
have concentrated on the basic elements and the structural forms of
describing models in VHDL. In this module we concentrate on the
behavioral view, that is, describing how the circuit is to perform.
We hide the structure of the design when modeling a circuit
behaviorally. Instead, we are vitally interested in the functionality
of the circuit. At the highest levels of abstraction, we even ignore
timing.
When modeling in VHDL it is important to follow standard practices of
software engineering. Otherwise, the model will be hard to maintain,
even by the person who wrote it. In addition, to aid the reuse of
models, even "throw-away" models should be created with care, and
with the thought that others may use it.
Typical model design and coding practices include structuring the
design, iteratively refining a high-level view of the model down to
its final form, employing abstract data typing to hide and encapsulate
data, and organizing the individual model components so that they are
loosely coupled (small number of interface signals) and have strong
cohesion (keep strongly related functions in the same architectural
body).
