ARCHITECTURE test_generate OF test_entity IS
SIGNAL S1, S2, S3 : BIT_VECTOR (7 DOWNTO 0);
BEGIN
G1 : FOR N IN 7 DOWNTO 0 GENERATE
G2 : IF (N=7) GENERATE
or1 : or_gate
GENERIC MAP (3ns, 3ns)
PORT MAP (S1(n), S2(N), S3(N));
END GENERATE G2;
G3 : If (N < 7) GENERATE
and_array : and_gate
GENERIC MAP (2ns, 3ns)
PORT MAP (S1(N), S2(N), S3(N));
END GENERATE G3;
END GENERATE G1
END test_generate;
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