The GENERIC MAP is similar to the PORT MAP in that it maps specific values to generics declared in the component
PACKAGE my_stuff IS
COMPONENT and_gate
GENERIC (tplh, tphl : time);
PORT (in1, in2 : IN BIT; out1 : OUT BIT);
END COMPONENT;
END PACKAGE my_stuff;
USE Work.my_stuff.ALL;
ARCHITECTURE test of test_entity IS
SIGNAL S1, S2, S3 : BIT;
BEGIN
Gate1 : my_stuff.and_gate
GENERIC MAP (2ns, 3 ns)
PORT MAP (S1, S2, S3);
END test;