Uses of Generate Statement

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Structural descriptions can more clearly indicate the nature of the physical hardware used to create the component. However, several digital devices have large regular structures that can be tedious to implement. Using a behavioral description or a long structural description could mask the regular structure of these devices.

VHDL provides the GENERATE statement to automatically create such structures. The GENERATE statement can be used in conjunction with any VHDL concurrent statement to create many repetitive objects. A GENERATE statement may even include other GENERATE statements for more complex devices. Some common examples include the instantiation and connection of multiple identical components such as half adders to make up a full adder, or exclusive or gates to create a parity tree.