Sequential Signal Assignments

Signals can be both sequential and concurrent statements

Signals require a delay even with sequential execution

ARCHITECTURE test1 OF test_mux IS
     SIGNAL a: BIT := '1';
     SIGNAL a: BIT := '0';
BEGIN
     PROCESS (...)
     BEGIN
       a <= b;
       b <= a;
     END PROCESS;
END test1;

What are the final signal values for a and b in this case?

Multiple assignments to the same signal in a PROCESS are allowed

ARCHITECTURE test1 OF test_mux IS
     SIGNAL a : BIT;
BEGIN
    PROCESS
     BEGIN
        a <= '1';
        a <= '0';
     END PROCESS;
END test1;

What is the value of a at the end of this process?