Getting Started
Tutorial Purpose
Effective top-down design using VHDL is critical in order to
realize reductions in the development time and cost of complex
digital electronic systems. The purpose of this interactive
VHDL tutorial is to help designers learn how to effectively
use VHDL to design complex digital electronic systems. To
support this learning process, the tutorial is organized
around four related modules that are designed to incrementally
add to your understanding of the VHDL language and its
application. By integrating these modules with the VHDL
Language Reference Manual, IEEE Standard 1076-1993, (VHDL LRM) in a hypertext
environment, we believe that this interactive tutorial will
not only help you to learn the language but will provide a
useful reference to you as you progress from novice to expert.
Each module is organized as a set of hyper-linked slides. A
MAP link for each module is provided that presents a graphical view
of the topics discussed in the module. An INDEX link
is provided that enables hyper-linked access to any topic area
or slide within a module. At the top of most pages are the IEEE VHDL LRM icon
and the VHDL Interactive Tutorial Home Page icon.
The linked IEEE VHDL LRM icon will always return you to the VHDL LRM Table of Contents and the linked
VHDL Interactive Tutorial Home Page icon will always return you to the tutorial home page.
Together these links provide easy access to any material that may be of interest.
For a graphical introduction to the modular tutorial page layout and links, click here.
Sponsorship
This VHDL Interactive Tutorial was initiated as part of the RASSP
Education & Facilitation (RASSP E&F) effort with support from the
Defense Advanced Research Projects Agency Electronics Technology Office (DARPA/ETO) and
United States Air Force Wright Aeronautical
Laboratory under contract number F33615-94-C-1457. Rapid Prototyping of Application
Specific Signal Processors (RASSP) is a major DARPA/Tri-Service
initiative to reinvent the process by which embedded digital
signal processors are developed. The goal is a four-fold reduction in the time from concept
to fielded prototype on both new designs and design upgrades, with similar improvements in
life cycle cost, quality and supportability. More information on RASSP may be obtained from
the RASSP web site (http://rassp.scra.org).
Module Abstracts
This tutorial is organized into four modules. If you have little or no VHDL experience, the modules should be
reviewed in order to provide the background material necessary for the next section. The modules are numbered for
easy reference and start at one. The abstract information below provides a synopsis of each module.
The Basic VHDL module (module 1) is
an introduction to the VHSIC Hardware Description Language and its fundamental concepts. VHDL is a
language specifically developed to describe digital electronic hardware and its attributes. VHDL is a flexible
language and can be applied to
many different design situations. This language has several key advantages,
including technology independence and a standard language for
communication. The module describes many
of the advantages of using VHDL and a short history of the language.
The Structural VHDL module (module 2) describes the use of VHDL for describing models in terms of component instantiations and interconnections.
Structural VHDL can be appropriate at any level of design. For example, testbenches for completed components are often described using
structural VHDL. Furthermore, structural VHDL supports the use of libraries and component reuse. This module first describes the process of
creating, or instantiating, a component for simulation. A component instantiation declares a component ready for use in the architecture and
specifies key parameters, if necessary. The generate statement is capable of creating regular structures automatically, such as RAM and ROM.
Thus, the generate statement can eliminate some repetitiveness when dealing with such structures. Additionally, this module shows how VHDL
supports libraries and component reuse. Components in structural VHDL are fully described outside the architecture, most often in component
libraries. Configuration of these components involves selecting an entity and architecture for the component and specifying parameters for the
component. The Structural VHDL module does not include a large, comprehensive example. However, an example highlighting the use of each
VHDL construct is provided. Structural VHDL supports libraries and design partitioning through configuration; this module shows the VHDL
constructs supporting these concepts.
The Behavioral VHDL module (module 3) describes features of the language that describe the behavior of components in response to signals. Behavioral
descriptions of hardware utilize software engineering practices and constructs to achieve a functional model. Timing information is not
necessary in a behavioral description, although such information certainly can be added. The VHDL constructs in this module focus on
describing hardware utilizing software engineering practices. The VHDL process construct is described first. Processes run code in a top to
bottom fashion, similar to a computer program. The types of statements allowed in a process, referred to as ’sequential’ statements, are listed.
Subprograms are another behavioral construct, allowing for code reuse and simplification. One use of subprograms is in bus resolution
functions. These important functions allow the use of buses with multiple signal drives in VHDL models. Packages are another useful VHDL
feature in behavioral modeling. Packages can contain the code for subprograms as well as often used custom data types. Finally, the module
describes the use of testbenches and lists some problems to avoid in VHDL. The Behavioral VHDL module ends with a comprehensive example
using the SDSP microprocessor. The details of this microprocessor are not relevant to this module, but some of the underlying code is shown
for instructional purposes. Several subprograms that implement basic processor functions, such as the add function, are shown. Additionally,
the testbench and some control program code is shown. This example shows the many uses of behavioral VHDL.
The System Level VHDL module (module 4) covers a wide range of topics, focusing on VHDL constructs as applied to higher levels of design abstraction.
A definition of ’system’ is presented for purposes of this module along with several key concepts. This module is not intended for the
instruction of system level design; rather, this module focuses on the usefulness of VHDL at the system level. Therefore, some time is also
spent on the many advantages of using VHDL at this level. This module also presents uninterpreted modeling using VHDL, as this type of
modeling is frequently used at higher levels. The VHDL constructs supporting the system level design are described next. The first group of
constructs provides abstract data types to the designer. Using records and aliases, the designer can implement data types, such as ’tokens’,
that are important for uninterpreted modeling. Shared variables allow for sharing data among processes and the TEXTIO package allows the
design to process files for input and output. Finally, the use of VHDL in object oriented design is shown. Using VHDL in object oriented design
has several advantages over other methods. Finally, two comprehensive examples showing the use of VHDL at the system level are provided.
The first example, using the University of Virginia's ADEPT system, shows the use of records and abstract data types to implement Petri Net
models using VHDL. Extensive use of functions and procedures shows the power of subprograms in VHDL. The Honeywell PML provides
another example of system level VHDL. The Honeywell PML models computer components at the uninterpreted level and can consider various
bus types. Together, these examples show the use of VHDL in a complex system level design.