Creating FPGA /CPLD Designs with Active-VHDL

Introduction

This application note describes a typical approach to FPGA and CPLD designing in Active-VHDL. The document does not focus on any specific FPGA or CPLD vendor. Detailed guidance on designing for different vendors is the subject of vendor-specific tutorials.

Resource Files

A typical FPGA /CPLD design contains resource files (source files, SDF files, macro files, etc.) created at different stages of the design process. To clarify the design contents, consider dividing the resource files into groups stored in separate folders in the Design Browser. An exemplary grouping can be as follows:

• Folder Functional groups files created at the initial stage of the design process. It includes source files intended for synthesis and test benches.
• Folder Timing groups files obtained from the Place and Route tools. They are used for timing simulation and usually comprise:

• Structural VHDL files modeling the physical netlist.
• SDF files containing timing data used to annotate timing models.

• Folder Simulate groups macro files (macro files contain batches of Active-VHDL commands) launching functional and timing simulations.
• Folder Implement groups macro files used to launch synthesis and place-and-route programs (see section Synthesis).

The Design Browser allows you to create any number of folders with any names. The name of a folder does not imply its destination.

The figure below shows the folders as discussed in the text.

Functional Simulation

The initial VHDL description of the design undergoes functional verification in the VHDL simulator. The key issue at this stage of the design process is creation of appropriate test vectors. Test vectors provide stimulus for the model inputs and forces the model to produce the output response. Evaluation of the output response provides the answer to whether the model’s behavior satisfies the designer’s expectations or not.

In Active-VHDL, you can apply stimulus to the input models in three different ways:

• By using the Stimulators tool in the Waveform window. The dialog supports several different techniques of defining the stimulus waveforms. The contents of the Waveform window is eventually saved to a file. Waveform files will be used later on in other simulations and to generate test bench files.
• By creating a macro file containing sequences of force commands.
• By creating a test bench file. A test bench file contains a design entity being a host environment for the tested design entity. Depending on the degree of its complexity, the test bench can automatically produce input stimulus and compare the output response with previously defined pattern output vectors.

Creating Test Benches

The figure below illustrate the concept of a test bench.

The process implemented in the architecture body of a test bench should force desired stimulus on the inputs of the tested design unit (Unit Under Test = UUT) to enable functional verification of the design. In addition, advanced test benches can also perform comparison of the obtained output response with a previously defined pattern.

Active-VHDL supports automatic generation of test benches on the basis of waveforms previously created in the Waveform window and saved to a file. The test bench file contains a test bench entity declaration and its architecture body. The architecture body contains:

• Component instantiation for the UUT entity.
• Local signals mapped to ports of the UUT entity.
• A process statement that forces stimulus on the local signals connected to input ports of the UUT entity. This statement is included only if a waveform file was specified as a source of test vectors. Otherwise, the user has to supply appropriate process by himself.

It is usually possible to re-use in timing simulation a test bench created for functional simulation. The shortest way to do so is to write a configuration declaration that binds to the UUT entity the architecture body obtained from the Place and Route tool. Such an approach is applicable only if the entity obtained from the Place and Route tool matches the UUT entity in the initial VHDL description in respect of ports and generics.

Synthesis

After the design has been verified in functional simulation, it should be synthesized in order to obtain a netlist for physical implementation. Active-VHDL itself does not provide any interface to synthesis tools. However, the user can write macros that will call external programs and pass data to and from them. Moreover, it is possible to extend the macro language by adding user-defined basic scripts that implement new commands. In this way, it is possible to create a user-customizable interface to external synthesis and Place-and-Route tools. The only restriction arises from the fact that the external programs are called along with parameter specification from the command line. Not all programs can work in such a mode.

Different synthesis tools have their specific sets of options. The information of these options is available in proprietary documentation for these tools.

Some synthesis tools can export synthesized netlist into VHDL. Simulation of so obtained VHDL code and comparison with results from the simulation of the initial description gives you additional verification of the design.

Active-VHDL can be used along with Active CAD. Active CAD provides interface to a variety of synthesis and Place and Route tools in a wide range of vendors (Actel, Altera, Lucent, Lattice, QuickLogic, Xilinx) and target devices. Active CAD can export a project into VHDL. During the export, the project netlist (pre-routed) is converted into VHDL and a new design is created in the Active-VHDL-compatible format.

Implementation

The netlist produced by synthesis tools is an input for Place and Route tools. The final result of running of a Place and Route tool is a bitstream file that can be downloaded into a programmable FPGA device. Most tools can generate VHDL model of the implemented design for timing simulation. The model is structural and based on primitive models supplied in the vendor-provided VHDL libraries. Appendix A provides a list of vendor-specific libraries shipped with Active-VHDL.

Most libraries with timing primitive models are based on VITAL procedures.

Primitive models used for timing simulation possess a set of timing parameters (passed on to the model through generics). Two methods are applicable to define value of these generics:

• The actual values are defined directly in the VHDL code by generic map aspect.
• The actual values are specified in separate files in the SDF (Standard Delay Format) format.

Adding Post-Place-and-Route Files to Design

Using the Design Browser you have to attach to the design the files obtained from the Place and Route tool. These files usually are:

• VHDL file(s) containing a structural model for timing simulation.
• SDF file(s) containing timing parameters (if SDF generation is supported).

You can also create a brand new design for files obtained from the Place & Route tool.

Compiling of Post-Place-and-Route VHDL Code

The VHDL file generated by Place-and-Route tools contains an entity-architecture pair (design entity) describing the design implemented in an FPGA /CPLD device. In general, the entity and architecture in the generated file can have any names. Note that if these names are identical to those of the design units in the initial design description, compilation of the post-Place-and-Route files will cause that some design units will be overwritten in the default design library.

It is also important that the ports of the post-Place-and-Route entity matches those of the entity in the initial description.

Timing Simulation

To simulate the timing model obtained from the Place and Route tool, you have to:

• Select the entity-architecture pair from the post Place-and-Route file.
• If the Place-and-Route tool has generated SDF files, you should attach them to the design. Before the initialization of simulation, assign SDF files to corresponding regions of the design using the Design Settings dialog (menu Design, command Settings). The dialog (see figure below) automatically displays all SDF files attached to the design. For each file you can individually specify the design region and the set of timing parameters to load (min, typ, max). You can selectively enable or disable loading of specific SDF files. For the top-level entity, use slash (/).

Note that SDF annotation must be performed before initialization of simulation.

Creating VHDL for Synthesis

• When you create a model intended for synthesis, you should have in mind a general notion of its structure. If you employ the same approach as for behavioral modeling, the resulting VHDL code may contain constructs that are not acceptable for synthesis tools. Moreover, if the synthesis of so created model will be successful, the results of functional simulation of such a netlist in a gate level simulator may differ from the results of VHDL simulation of the initial model. This results from the fact that:

• Synthesis tools impose specific constraints on the range of available VHDL constructs and contexts in which they can appear.
• Synthesis tools infer the logic also from the context in which specific VHDL constructs appear.

• Before you begin writing the VHDL code, consult documentation of the tool you are going to use for the logic synthesis.
• Test bench files are intended only for simulation so they do not have to comply with the constraints imposed on VHDL syntax by synthesis tools.
• Each synthesis tool provides packages with functions, procedures and attributes useful in creation of synthesizable models. Particularly, attributes defined in such packages are used to pass specific information to the synthesis tool (e.g. the pin numbers, machine encoding methods, etc).
• If a design is targeted for an FPGA /CPLD device of specific vendor, you can use libraries of functional modules and primitives prepared by this vendor. For most vendors, Active-VHDL provides libraries in the compiled format. By adding appropriate library and use clauses into your VHDL files, you can use modules contained in these libraries. Appendix A contains a list of all vendor-specific libraries shipped with Active-VHDL.
• In addition to libraries of modules, some Place and Route tools also accept parameterized modules. Parameterized modules can be instantiated directly by the user in the VHDL code, or by synthesis tools in the netlist.

Appendix A
Vendor-specific libraries of simulation primitives

ACTEL

A3200DX - functional and post-place-and-route simulation library for 3200DX family

ACTEL1 - functional and post-place-and-route simulation library for ACTEL1 family

ACTEL2 - functional and post-place-and-route simulation library for ACTEL2 family

ACTEL3 - functional and post-place-and-route simulation library for ACTEL2 family

ALTERA

ALT_VTL - post-place-and-route simulation library

CYPRESS

CYPRESS_FUNCTIONAL (for CPLD/ FPGA) - functional component library with arithmetical packages.

PRIMITIVE (for CPLDs) - post-place-and-route simulation library

QLPRIMS (timing models for PASICs) - post- place-and-route simulation library

LATTICE

LAT_VHD - functional component library

LAT_VITL - post-place-and-route simulation library

LUCENT

ORCA - functional component library

NEOPRIMS - post-place-and-route simulation library

Quick Logic

QLOGIC_FUNCTIONAL - functional component library

QLPRIMS - post-place-and-route simulation library

XILINX

XU - functional component library

SIMPRIM - post-place-and-route simulation library

Except for CYPRESS_FUNCTIONAL and PRIMITIVE, all libraries mentioned above are based on standard VITAL procedures and are shipped with the vendor’s software.

Appendix B
Block Diagram of Processing of FPGA /CPLD Designs