Using Active-VHDL for Active-CAD Designs

Introduction

Active-CAD is a suite of tools used to develop FPGA /CPLD designs. It supports different methods of design description. A design in Active-CAD can be described by a schematic built of components from a vendor-specific library (schematic-based designs) or by synthesizable VHDL code (top-level VHDL designs). Schematic-based designs can also include partial VHDL description as VHDL macros.

Functional simulation in Active-CAD is always based on the netlist generated from the design schematic or, in case of purely VHDL designs, obtained from synthesis. VHDL macros instantiated in schematic-based designs have also to be synthesized before simulation in order to obtain the macro netlist.

Note that even in case of purely VHDL-based designs, the functional simulation is based on the synthesized netlist rather than on the VHDL code. Errors can be detected only after synthesis, which inhibits effective and quick debugging of the design. Here, you can employ Active-VHDL with its VHDL simulator. You can simulate VHDL code used in Active-CAD designs. Moreover, you can export schematics into VHDL. To facilitate moving designs to Active-VHDL, Active-CAD provides a simple mechanism for exporting the design netlist into VHDL.

Schematics and VHDL Simulation

A schematic can be verified by means of VHDL simulation provided that its netlist will be exported into VHDL. A VHDL code obtained from a schematic is fully structural and represents the exact structure of the netlist of the exported schematic.

The netlist of a flat (non-hierarchical) schematic is built solely of primitives (gates, flip-flops, etc.). The VHDL code (contained in a single file) exported from such a netlist consists of components interconnected with signals. Signals correspond to wires (both discrete wires and buses). Component instantiations correspond to primitives in the netlist. A design library containing simulation models for all primitives is required for the simulation of the exported VHDL code.

The netlist of a hierarchical schematic is hierarchical. In addition to the main VHDL file describing the top-level schematic, separate VHDL files are generated for hierarchical macros. A single VHDL file is generated for each macro identified by a unique name, irrespective of the number of instances in which the macro occurs in the design.

Exporting an Active-CAD Design into VHDL

When you export an Active-CAD design into VHDL, the following operations are performed:

• A new directory, named VHDL, is created inside the directory of the exported design. All files generated during the export are placed into this directory.
• For each schematic macros, two files named the same as the macro are generated:

• a VHDL file with structural description corresponding to the schematic netlist (extension VHD)
• an auxiliary text file containing a list with original identifiers modified during the export (extension LOG). Renaming of identifiers takes place when some schematic items use names that are reserved words in VHDL. For example, if a signal is named OUT, it will be automatically renamed because out is a VHDL reserved word denoting the direction of a port.

• For VHDL macros, their source VHDL files are copied to the VHDL directory.
• For state diagram macros, their diagram files (*.ASF) and VHDL files (if available) are copied into the VHDL directory.
• A text file VHDL.LST is generated containing a list of *.ASF and *.VHD files that have been copied into the VHDL directory.

Customizing Export to VHDL

Due to the variety of design types supported by Active-CAD, the export operation can be flexibly customized by the user. Configuration settings are defined individually for each design type (flow type) and stored in configuration files in the ACTIVE\VHDL directory. The VHDL.CFG file includes an index of configuration files.

Libraries of Simulation Models in Active-VHDL

The VHDL code exported from Active-CAD designs contains instances of components whose simulation models must be included in one of the VHDL libraries available in Active-VHDL. Active-VHDL provides compiled libraries of simulation models for most FPGA and CPLD. Sources for these libraries are offered by some vendors, however, they should not be modified nor recompiled by the user.

Active-VHDL provides libraries for the following vendors:

• ACTEL (all families)
• LATTICE
• LUCENT
• QuickLogic
• XILINX

VHDL code exported from design of types listed above can be simulated in Active-VHDL without any additional user’s adjustments

Moving a Design from Active-CAD to Active-VHDL

Steps described below outline a typical procedure the user follows in order to move a design to Active-VHDL and perform functional simulation:

1. Develop the design in Active-CAD. The design can be of the schematic-based type (optionally with VHDL and state diagram macros) or of the top-level VHDL type.
2. Export the design to VHDL using the Export Design to VHDL command from the Tools menu in the Active-CAD Project Manager. The VHDL directory will be created in the design directory of the exported Active-CAD design.
3. Run Active-VHDL and open the PDF file of the Active-CAD design. This operation results in the following:

• An Active-VHDL design is created in the VHDL directory, which includes setting up a directory named the same as the exported design and creating the ADF file. The ADF file in Active-VHDL is a functional counterpart of the PDF file in Active-CAD. For example, if an original Active-CAD design has been stored in the \ACTIVE\PROJECTS\CALC directory, the Active-VHDL design will reside in the directory \ACTIVE\PROJECTS\CALC\VHDL\CALC.
• Files created in the VHDL directory are attached to the Active-VHDL design. Note that these files reside outside the directory of the Active-VHDL design and their icons displayed in the Design Browser have the mark.

4. Compile all source files in the design with the automatic file reorder. The automatic reorder ensures that the files are compiled in the sequence implied by dependencies between these files.
5. Select the top-level entity and initialize simulation.

NOTE: Any changes introduced to the design in Active-CAD cause that the design must be exported again and recompiled.

Using Test Vectors from Active-CAD in Active-VHDL

If the exported design has been previously simulated in Active-CAD, simulation test vectors are usually available. You can re-use them for simulation in Active-VHDL. Test vectors must be saved in the ASCII format (Active-CAD uses two formats of test vector files: binary and ASCII). In addition to signal waveforms, the ASCII files include information about stimulators as they have been defined in the Waveform window.

To re-use test vectors from Active-CAD:

• In Active-CAD, save waveforms in the ASCII format. Use the File /Save Waveform command with setting the type of the file to ASCII Test Vectors.
• In Active-VHDL, open the file using the File /Open menu command. The operation will restore waveforms as they have been saved in the file and convert stimulators specification to the Active-VHDL format.

Simulating macros of other types in Active-VHDL

Active-CAD allows you to use macros of other type than schematic and VHDL (ABEL macros, Verilog macros, XBLOX macros, macro generated by the MEMGEN program). Simulation of such a macro in Active-VHDL is possible provided that the macro netlist is built of components whose simulation models are available in libraries in Active-VHDL. For example, ABEL macros occurring in XACTStep M1 designs cannot be simulated in Active-VHDL because their netlist is based on components from a specific library, XABELSIM, that has no counterpart in Active-VHDL libraries.

Notes and Knows Problems

Simulation results obtained with Active-VHDL may sometimes differ from those obtained with Active-CAD simulator. The possible causes of such discrepancies can be as follows:

• Behavior of simulation models in Active-CAD and Active-VHDL differs in the power-on initialization, for example, the output of the FDC flip-flop used in Xilinx designs after initialization assumes ‘X’ in Active-VHDL and ‘0’ in Active-CAD.
• Simulation models in Active-VHDL can use default propagation delay values different from 0. In Active-CAD functional simulation is always performed with zero delay values.
• Use of the SimGlobalReset signal in Active-CAD simulator makes no sense because the VHDL code generated from such a design does include such a signal.
• VHDL macros in a Active-CAD design have port types different that STD_LOGIC or STD_LOGIC_VECTOR