8-4 BUS STANDARDS
The Intel MULTIBUS has gained wide industrial acceptance
and several manufacturers offer MULTIBUS-compatible
modules. This bus is designed to support both 8-bit and
16-bit devices and can be used in multiprocessor systems
in which several processors can be masters.
At any point in time, only two devices may communicate with
each other over the bus, one being the master and the
other slave. The master/slave relationship is dynamic
with bus allocation being accomplished through the bus
allocation (i.e. request/grant) control signals. The
MULTIBUS has been physically implemented on an etched
backplane board which is connected to each module using
two edge connectors, denoted P1 and P2, as shown in
Fig.8-20.
The connector P1 consists of 86 pins which provide the
major bus signals, and P2 is an optional connector
consisting of 60 auxiliary lines.
The P1 lines can be divided into the following groups
according to their functions:
- Address lines.
- Data lines.
- Command and handshaking lines.
- Bus access control lines.
- Utility lines.