The 8259A has an even address (A0=0) and an odd address
(A0=1) associated with it and the initialization command
words must be filled consecutively by using the even
address for ICW1 and the odd address for the remaining
ICWs.
The definitions of the bits in ICW1 are:
- Bits 7-5- Not used in an 8086/8088 system, only
in an 8080 or 8085 system.
- Bit 4- Always set to 1. It directs the
reveived byte to ICW1 as opposed to )CW2 or OCW3, which
also use the even address (A0=0).
- Bit 3 (LTIM)- Determines whether the
edge-triggered mode (LTIM=0) or the level-triggered mode
(LTIM=1) is to be used. The edge-triggered mode causes the
IRR bit to be cleared when the corresponding ISR bit is set.
- Bit 2 (ADI)- Not used in an 8086/8088 system,
only in an 8080 or 8085 system.
- Bit 1 (SNGL)- Indicates whther or not the
8259A is cascaded with other 8259A. SNGL=1 when only
one 8259A is in the interrupt system.
- Bit 0 (IC4)- Is set to 1 if an ICW4 is to be
output to during the initialization sequence. For an 8086/8088
system this bit must always be set to 1 because bit 0
in ICW4 must be set to 1.
Bits 7-3 of ICW2 are filled from bits 7-3 of the second
byte output by the CPU during the initialization of the
8259A and bits 2-0 are set according to the level of the
interrupt request, e.g. a request on IR6 would cause them
to be set to 110. ICW3 is significant only in systems
including more than one 8259A and is output to only if
SNGL=0. This case is discussed in Sec.8-3-2. ICW4 is
output to only if IC4 (ICW1) is set to 1, otherwise, the
contents of ICW4 is cleared. The bits in ICW4 are
defined as follows:
- Bits 7-5- Always set to 0.
- Bit 4 (SFNM)- Is set to 1, the special fully
nested mode is used. This mode is utilized in systems
having more than one 8259A and is discussed below.
- Bit 3 (BUF)- BUF=1 indicates the /SP / /EN is
to be used as an output to disable the system's 8286
transceivers while the CPU inputs data from the 8259A.
If no transceivers are present, BUF should be set to 0 and in
systems involving only one 8259A a 1 be applied to the
/SP / /EN pin.
- Bit 2 (M/S)- This bit is ignored if BUF=0.
For a system having only one 8259A, this bit should be 1;
otherwise, it should be 1 for the master and 0 for the
slaves.
- Bit 1 (AEOI)- If AEOI=1, then the ISR bit that
caused the interrupt is cleared at the end of the second /INTA
pulse.
- Bit 0 (uPM)- uPM=1 indicates the 8259A is in
an 8086/8088 system. This bit being 0 inplies an 8080 or 8085
system.
A typical program sequence for setting the contents of the
ICWs, which assumed that the even address of the 8259A is 0080
is:
MOV AL, 13H
OUT 80H, AL
MOV AL, 18H
OUT 81H, AL
MOV AL, 0DH
OUT 81H, AL
The first two instructions cause the requests to be
edge-triggered, denote that only one 8259A is used, and
inform the 8259A that an ICW4 will be output. The next two
instructions cause the 5 most significant bits of the
interrupt type to be set to 0011. ICW3 is not output to
because SNGL=1; therefore, the last two instructions set
ICW4 to 0DH, which informs the 8259A that the special
fully nested mode is not to be used, the /SP / /EN is
used to disable transceivers, the 8259A is a master,
EOI commands must be used to clear the ISR bit, and the
8259A is part of an 8086/8088 system.
There are three OCWs. The command word OCW1 is used for
masking interrupt requests; when the mask bit corresponding
to an interrupt request is set to 1, then the request is
blocked. OCW2 and OCW3 are for controlling the mode of
the 8259A and receiving EOI commands.