I/O INTERFACE

As an example, consider an 8272 whose even address is 002A.The 8272 could be initialized to a step rate of 6 ms per track, a head unload time of 48 ms, a head load time of 16 ms and the DMA mode by the specify command sequence

                    %CHECK (2AH,80H)
                              MOV   AL,03H
                              OUT   2BH,AL  
                    %CHECK (2AH,80H)
                              MOV   AL,63H
                              OUT   2BH,AL 
                    %CHECK (2AH,80H)
                              MOV   AL,10H
                              OUT   2BH,AL

where the macro CHECK is defined as follows:

            %DEFINE  (CHECK (PORT,STAT))  LOCAL AGAIN
            (%AGAIN:  IN   AL,%PORT
                      AND  AL,0C0H
                      XOR  AL,%STAT
                      JNE  %AGAIN
            )

The reason the %CHECK macro is needed before each output is that the two MSBs of the status register must be 10 before each command byte is written into the 8272.Also during the result phase, these 2 bits must be 11 before each byte is read from the 8272's data register.

                    %CHECK (2AH,80H)
                              MOV   AL,0FH
                              OUT   2BH,AL  
                    %CHECK (2AH,80H)
                              MOV   AL,02H
                              OUT   2BH,AL 
                    %CHECK (2AH,80H)
                              MOV   AL,30
                              OUT   2BH,AL

would cause the head on drive 2 to be moved to cylinder 30 and head 0 to be selected.

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