_ __     __
 The 8251A internally interprets the C/D,RD and WR signals as follow:
   _         __     __ 
 C/D(=Ao)    RD     WR
    
    0        0      1     Data input from the data-in buffer 
    0        1      0     Data output to the data-out buffer
    1        0      1     Status register is put on data bus
    1        1      0     Data bus is put in mode, control
                           or sync character register

 Whether the mode, control or sync character register is selected depends on
the accessing sequence.A flowchart of the sequencing is given in Fig. 9-14.