Figure 2-21 Examples of instruction execution times.
| Instruction | No. of Clock Cycles | No. of Transfers | |||
|---|---|---|---|---|---|
| ADD (addition) or SUB (subtraction) | |||||
| Register to register | 3 | 0 | |||
| Memory to register | 9+EA | 1 | |||
| Register to memory | 16+EA | 2 | |||
| Immediate to register | 4 | 0 | |||
| Immediate to memory | 17+EA | 2 | |||
| MOV (move) | |||||
| Accumulator to memory | 10 | 1 | |||
| Memory to accumulator | 10 | 1 | |||
| Register to register | 2 | 0 | |||
| Memory to register | 8+EA | 1 | |||
| Register to memory | 9+EA | 1 | |||
| Immediate to register | 4 | 0 | |||
| Immediate to memory | 10+EA | 1 | |||
| Register to segment register | 2 | 0 | |||
| Memory to segment register | 8+EA | 1 | |||
| Segment register to register | 2 | 0 | |||
| Segment register to memory | 9+EA | 1 | |||
| MUL (unsigned multiply) | |||||
| 8-bit register multiplier | 70-77 | 0 | |||
| 16-bit register multiplier | 118-133 | 0 | |||
| 8-bit memory multiplier | (76-83)+EA | 1 | |||
| 16-bit memory multiplier | (124-139)+EA | 1 | |||
| IMUL (signed multiply) | |||||
| 8-bit register multiplier | 80-98 | 0 | |||
| 16-bit register multiplier | 128-154 | 0 | |||
| 8-bit memory multiplier | (86-104)+EA | 1 | |||
| 16-bit memory multiplier | (134-160)+EA | 1 | |||
| DIV (unsigned divide) | |||||
| 8-bit register divisor | 80-90 | 0 | |||
| 16-bit register divisor | 144-162 | 0 | |||
| 8-bit memory divisor | (86-96)+EA | 1 | |||
| 16-bit memory divisor | (150-168)+EA | 1 | |||
| IDIV (signed divide) | |||||
| 8-bit register divisor | 101-112 | 0 | |||
| 16-bit register divisor | 165-184 | 0 | |||
| 8-bit memory divisor | (107-118)+EA | 1 | |||
| 16-bit memory divisor | (171-190)+EA | 1 | |||
| Shift and rotate instructions | |||||
| Single-bit register | 2 | 0 | |||
| Variable-bit register | 8+4/bit | 0 | |||
| Single-bit memory | 15+EA | 2 | |||
| Variable-bit memory | 20+EA+4/bit | 2 | |||
| JMP (unconditional branch) | |||||
| Short | 15 | 0 | |||
| Intrasegment direct | 15 | 0 | |||
| Intersegment direct | 15 | 0 | |||
| Intrasegment indirect using register mode | 11 | 0 | |||
| Intrasegment indirect | 18+EA | 1 | |||
| Intersegment indirect | 24+EA | 2 | |||
| Conditional branch instructions | |||||
| JCXZ | 6 (no branch) 18 (branch) | 0 | |||
| All other conditional branch instructions | 4 (no branch) 16 (branch) | 0 | |||
Figure 2-22 Times needed to calculate the effective address.
| EA | No. of Clock Cycles | ||
|---|---|---|---|
| Direct | 6 | ||
| Register indirect | 5 | ||
| Register relative | 9 | ||
| Based indexed | |||
| (BP)+(DI) or (BX)+(SI) | 7 | ||
| (BP)+(SI) or (BX)+(DI) | 8 | ||
| Based indexed relative | |||
| (BP)+(DI)+DISP or (BX)+(SI)+DISP | 11 | ||
| (BP)+(SI)+DISP or (BX)+(DI)+DISP | 12 | ||
This is page 21.