SimFlex – simulator has been developed at the department of Electrical and Com-puter Engineering at Carnegie Mellon University, USA. The SimFlex has two parts: Flexus and SMARTS. The Flexus is a powerful and flexible simulator framework that allows full-system simulation that relies heavily on well-defined component interface models to facilitate both model integration and compile-time simulator optimization. The SMARTS applies rigorous statistical sampling theory to reduce simulation turnaround by several orders of magnitude, while achieving high accuracy and confidence in estimates. This simulator enables component-based design and easy composition of in-order and out-of-order uniprocessor and multiprocessor models. The simulator has built-in statistics management and simulation state checkpointing. The Flexus is a family of component-based C++ computer architecture simulators that build on Virtutech Simics' Micro-Architecture Interface (MAI) to enable full-system timing-accurate simulation of uniprocessor and multiprocessor systems running unmodified commercial applications and operating systems. In its most detailed mode, each CPU that the Flexus simulates is as much as 100,000 times slower than actual hardware. However, Flexus’ functional warming mode is only 100 to 1,000 times slower than hardware, within a factor of 10 of Simics’ top speed. The SIMFLEX has been used to model both x86- and SPARC based uniprocessor and multiprocessor systems. The SIMFLEX, a simulation framework which uses component-based design and rigorous statistical sampling to enable development of complex models and ensure representative measurement results with fast simulation turnaround [51, 52, 53, 54]. This program can be used by software developers, students, testers, and performance analytics. The simulator has been used in computer architecture course for easy composition of in-order and out-of-order uniprocessor and multiprocessor models at Carnegie Mellon University.