In this section we focus on two orthogonal issues (often times misinterpreted as one single issue): (a) How to organize the teaching process (based on IEEE and ACM recommendations), and (b) How to conduct the teaching process (based on experience of the authors). a. How to organize the teaching process

A possible solution to course organization has been defined within the IEEE Computer Society and ACM Computer Engineering Task Force [1]. This task force has defined five mayor entities entitled: (a) Fundamentals of computer architecture, (b) Computer arithmetic, (c) Memory system organization and architecture, (d) Interfacing and communication, and (e) Organization of the CPU.

The first entity (Fundamentals of computer architecture) introduces basic topics like Registers and register file, Data types, Instruction types, Addressing modes, and Instruction formats. Each one should include explanations why a designer adopted a given different instruction formats, such as the number of addresses per instruction and variable length vs. fixed length formats. The next topic should explain how an instruction is fetched from memory and executed, with a special attention dedicated to Fetch, Decode, and Execution cycles. These lectures should also explain the organization of basic system and components and its major functional units. Students must also become familiar with the relationship between the representation of machine level operation at the binary level and their representation by a symbolic assembler. At this point student should be able to write small programs and fragments of assembly language code to demonstrate an understanding of machine level operations. Transformation of some fundamental high-level programming constructs to the machine-language level is one of the goals that should be achieved. At the end of this part of course, students are introduced to a variety of different I/O techniques and basic ideas connected to interrupt.

The entity Computer arithmetic should enable students to learn how numerical values are represented in digital computers, both integers (signed and unsigned) and real numbers. The integral part are basic arithmetic algorithms for integer operations, like addition, subtraction, multiplication, and division, and basic arithmetic algorithms for operations on real numbers. At the end of this entity students should be introduced to conversion between real and integer numbers. With this knowledge, students should understand the limitations of computer arithmetic and the effects of errors on calculation. This should help them understand issues related to the processor arithmetic unit and their impact on the overall computer performance. The third entity is Memory system organization and architecture, and it aims at explaining the methods for reduction of the effective memory latency and describing the principles of memory management. The next topic is the main memory organization, where students should identify the main types of memory technology, with basic concepts like latency, bandwidth, cycle time, and performance. That helps explain the impact of memory latency and bandwidth on performance. Students should be also introduced to the more sophisticated memory systems like virtual memory, cache memory, and memory interleaving. Beside logic construction, students should be introduced to some physical memory technologies like SRAM, DRAM, EPROM, Flash and at the end of this part of the course, to some aspects of reliability and error correction.

The next entity is Interfacing and communication. It should be explained to the students how interrupts are used to implement I/O control and data transfer, where terms like handshaking and buffering would be introduced. Immediately after that, basic I/O techniques like: programmed I/O, interrupt driven I/O, and DMA should be introduced. At this point, students should be able to write small interrupt service routines and I/O drivers using assembly language. The other topics connected to the interrupt are: vectored and prioritized, interrupt overhead, interrupts and reentrant code. In the next part of this entity students should be able to identify various types of buses in a computer system, like: control, address, and data buses, to understand bus clock cycles, and concepts of multi bus user using bus arbitration. The last part of this entity should concern concepts like parallel and serial interfaces. At this point students should be able to analyze and implement interfaces and timers.

The last entity entitled Organization of the CPU includes comparisons of alternative implementations of datapaths, plus studies of advantages and disadvantages of single vs. multiple bus datapaths. Within this topic, some advanced organizational details should be introduced like pipelined and non-pipelined systems, which should explain basic instruction level parallelism using pipelining and the major hazards that may occur. The next part of the entity focuses on the Control unit design, with special attention dedicated to the hardwired realization vs. microprogrammed realization. A discussion on the generation of control signals using hardwired or microprogrammed implementations should succeed. At the end of this entity, Arithmetic unit’s implementation should be introduced.