Introduction

This document contains the ISP description of the MIPS instruction set. Each instruction executes in 5 pipestages which have the following names:

Abbreviation Name Action
IF Instruction Fetch Starts fetching of the next instruction
ID Instruction Decode  
OD Operand Decode Address computation
SX Operand Store and Execute The operand leaves the register during this cycle. If the instruction has an ALU2 part it is executed during SX
OF Operand Fetch The fetched operand arrives from memory

A new instruction is started every two pipestages. Thus there are 3 instructions in execution once the pipeline has been filled.

IF ID OD SX OF            
    IF ID OD SX OF        
        IF ID OD SX OF    
            IF ID OD SX OF

A new instruction is fetched (logically) during the IF cycle. The program counter will have settled before the next (ID,SX) cycle. There are three ways to obtain the new program counter:

  1. An ALU operation with implicit destination "program counter" is executed. Such an operation can move the value from any register R0 through R15 into the program counter.
  2. The program counter is loaded with the destination of a jump or branch instruction.
  3. The program counter is incremented by one; this will happen if none of the other two options were used during (IF, OD, OF) cycle.

The old value of the program counter is stored in a 3-stage structure called PC(-1 - -3). The old value of PC(current) is stored in PC(-1); PC(-1) is stored in PC(-2) etc; the last value of PC(-3) is lost.

Instruction Stages
i-1 XXX OD SX OF            
i Store PC, $Return IF ID OD SX OF        
i+1 YYY     IF ID OD SX OF    
i+2 ZZZ         IF ID OD SX OF
i+3 AAA             IF ID OD
  PC(current) i   i+1   i+2   i+3   i+4

Figure 1

Note that PC(current) changes during the execution of an instruction. Figure 1 illustrates the situation (assume that instruction i-1 does not change the program counter): The value of i+3 is written to memory and stored in location $Return. Conditional branches can jam a new value into PC(current) during SX if the result of the test is "true". The next instruction will be fetched from the new location. This destination is computed during the OD stage of the branch instruction and kept in special register PC(+1) 

i 	beq #1,r1,$new
i+1 	xxx
i+2 	xxx

$new:k 	xxx
$new+1 	xxx

That is, if R1=1 the sequence of instructions executed is i, i+1, $new, $new+1, .. Note that:

	"beq #1, r1, $new"

will be assembled to "beq #1, r1, k-1" as PC(current) has already been incremented once at the time the destination address is computed.

Only PC(current) and PC(-3) are accessible via user instructions.

Privileged operations can be executed only if the processor is in supervisor state. A reserved operation must not be used; it can result in unpredictable behavior. A reserved operation will not be detected and no warning will be given. Opcodes which are not mentioned in this text are illegal and will be rejected.

A MIPS word has 32 bits; the bits are numbered from right to left. Bit 0 is the rightmost bit, and it is also the least significant bit. Bit 31 is the leftmost bit. A byte is an 8-bit quantity, therefore each word contains four bytes which are numbered from 0 to 3.

Byte 3 Byte 2 Byte 1 Byte 0

Integers are represented in two's complement; characters are stored in 8-bit fields, using the standard ASCII character set.

1. ALU3 + ALU2

00i'i dst alu.3 dst/src src alu.2 src2 src1

Instruction Format 

fmt<0:3>	::= instr <28:31>
i<0>		::= instr <28>
i'<0>		::= instr <29>
alu.3<0:3>	::= instr <20:23>
src1<0:3>	::= instr <0:3>
src2<0:3>	::= instr <4:7>
dst<0:3>	::= instr <24:27>
alu.2<0:3>	::= instr <8:11>
src<0:3>	::= instr <12:15>
dst/src<0:3>	::= instr <16:19>

Instruction Execution 

ALU23(::=fmt=0|fmt=1|fmt=2|fmt=3) --->
  ODU ---> (
 	 i' ---> Reg[dst] := OP2[alu.3](src1,Reg[src2]);
	~i' ---> Reg[dst] := OP2[alu.3](Reg[src1],Reg[src2])
	 );
  SXU ---> (
 	 i ---> Reg[dst/src] := OP2[alu.2](src,Reg[dst/src]);
	~i ---> Reg[dst/src] := OP2[alu.2](Reg[src],Reg[dst/src])
 	 );

Instruction Description A list of all fields for alu.3 appears in appendix 1. The operands indicated by registers src1 and src2 are operated on by the alu operation determined by the alu.3 field. If i' is one then src1 is used as an immediate value. The result of that operation is stored in the register indicated by dst.

A list of all fields for alu.2 appears in appendix 1. The operands indicated by registers dst/src and src are operated on by the alu operation determined by the alu.2 field. If i is one then src is used as an immediate value. The result of that operation is stored in the register indicated by dst/src.

2. Branch Conditionally

1111 000i cond src2 src1 12 bit signed offset

Instruction Format 

fmt<0:3> 	::= instr<28:31>
fmt2<0:3> 	::= instr<24:27>
cond<0:3> 	::= instr<20:23>
src2<0:3> 	::= instr<16:19>
src1<0:3> 	::= instr<12:15>
Offset<0:11> 	::= instr<0:11>
i<0> 		::= instr<24>

Instruction Execution 

BCND(::= fmt=15 & (fmt2=0|fmt2=1))->
  IDU ---> Disp := SignExtend(offset)
  ODU ---> PC(+1) := PC(current) + Disp;
  SXU ---> (
	 i ---> TEST[cond](src1,Reg[src2]) ---> PC(current) := PC(+1);
	~i ---> TEST[cond](Reg[src1],Reg[src2]) ---> PC(current) := PC(+1);
	 );

Instruction Description

The 12 bit offset is sign extended and added to PC(current) (which has been incremented once since this instruction was fetched). The result stored in PC(+1). The condition determined by cond is tested on the operands indicated by src1 and src2. The i field indicates whether src1 is to be interpreted as a literal or as a register. If the test is true then PC(+1) is jammed into PC(current).

3. Branch Unconditionally

1110 1110 24-bit signed offset

Instruction Format 

fmt<0:3> 	::= instr <28:31> 
fmt2<0:3> 	::= instr <24:27> 
Offset<0:23> 	::= instr <0:23>

Instruction Execution 

BUCND(::=fmt=14&fmt2=14) --->
  IDU ---> Disp := SignExtend(offset);
  ODU ---> PC(current) := PC(current) + Disp;

Instruction Description

The 24 bit offset is sign extended and added to PC(current) (which is currently at the next instruction) The result is stored in PC(current). Note that PC(current) is not incremented before the next instruction fetch is started.

4. Jump Based

1110 1101 base 20 bit signed offset

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<24:27> 
base<0:3> 	::= instr<20:23> 
offset<0:19> 	::= instr<0:19>

Instruction Execution 

JBASE(::= fmt=14 & fmt2=13) ---> 
  IDU ---> Disp := SignExtend(offset); 
  ODU ---> PC(current) := Reg[base] + Disp;

Instruction Description

The 20 bit offset is sign extended and added to the register indicated by base. The result is passed to PC(current). Note that PC(current) is not incremented before the next instruction fetch is started.

5. Jump Based Indirect

1110 1001 base 20 bit signed offset

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<24:27> 
base<0:3> 	::= instr<20:23> 
offset<0:19> 	::= instr<0:19>

Instruction Execution 

JBIND(::= fmt=14 & fmt2=9) ---> 
  IDU ---> Disp := SignExtend(offset); 
  ODU ---> MAR := Reg[base]+Disp; 
  OFU ---> PC(current) := Mp[MAR];

Instruction Description

The 20 bit offset is sign extended. This is added to the register indicated by base. The result is passed to the MAR. The contents of the memory location indicated by MAR are passed to PC(current). Note that PC(current) is not incremented before the next instruction fetch started.

6. Jump Based Indirect + ALU2

1110 010i base dst/src src alu.2 8 bit offset

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<24:27> 
base<0:3> 	::= instr<20:23> 
offset<0:7> 	::= instr<0:7> 
alu.2<0:3> 	::= instr<8:11> 
src<0:3> 	::= instr<12:15> 
dst/src<0:3> 	::= instr<16:19> 
i<0> 		::= instr<24>

Instruction Execution 

JIBALU(::= fmt=14 & (fmt2=4 | fmt2=5)) --->
  IDU ---> Disp:=SignExtend(offset); 
  ODU ---> MAR := Reg[base] + Disp; 
  SXU ---> (
	 i ---> Reg[dst/src] := OP2[alu.2](src.Reg[dst/src]); 
	~i ---> Reg[dst/src] := OP2[alu.2](Reg[src].Reg[dst/src]);
	 );
  OFU ---> PC(current) := Mp[MAR];

Instruction Description

The 8 bit offset is sign extended. This is added to a base register and the result is passed to the MAR. The content of this memory location are passed to PC(current). Note that PC(current) is not incremented before the next instruction fetch started.

A list of all fields for alu.2 appears in appendix 1. The indicated ALU operation is performed during the execution phase of the instruction. The i field indicates whether the source field should be interpreted as a 4 bit literal or to indicate a register. The second operand is also the destination of the operation.

7. Jump Direct

1110 1100 24 bit signed address

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<24:27> 
Address<0:23> 	::= instr<0:23>

Instruction Execution 

JDRCT(::= fmt=14 & fmt2=12) --->
  IDU ---> Disp := SignExtend(Address);
  ODU ---> PC(current) := Disp

Instruction Description

The 24 bit address is sign extended. This is passed to PC(current). Note that PC(current) is not incremented before next instruction fetch is started.

8. Jump Indirect

1110 1000 24 bit signed address

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<24:27> 
Address<0:23> 	::= instr<0:23>

Instruction Execution 

JIND(::= fmt=14 & fmt2=8) ---> 
  IDU ---> Disp := SignExtend(Address); 
  ODU ---> MAR := Disp 
  OFU ---> PC(current) := Mp[MAR];

Instruction Description

The 24 bit address is sign extended. This is passed to the MAR. The content of the memory location indicated by MAR is passed to PC(current). Note that PC(current) is not incremented before next instruction fetch is started.

9. Jump Indirect and Setup Su-register

1111 1111 24 bit signed address

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<24:27> 
Address<0:23> 	::= instr<0:23>

Instruction Execution 

JINDSS(::= fmt=15 & fmt2=15) --->
  IDU ---> Disp := SignExtend(Address);
  ODU ---> MAR := Disp
  OFU ---> PC(current) := Mp[MAR];

Instruction Description

The 24 bit address is sign extended. This is passed to the MAR. The content of the memory location indicated by MAR is passed to PC(current). Note that PC(current) is not incremented before next instruction fetch is started.

The SX cycle enables the SUregister. It will be used for the execution of all instructions which are fetched afterwards. (Therefore the instruction i+1 which follows the Jump-Indirect-and-Setup Instruction will not be affected. It has already been fetched during the OD cycle. Also note that the SU register will not be used during SX phase of instruction i+1. This cycle follows IF of (i+2) - where the SU register is used sequentially, but a multistage delay element will make sure that the value of SUregister is ignored for all phases of instruction i+1.)

10. Load Based

1001 dst.ld base 20 bit signed offset

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
dst.ld<0:3> 	::= instr<24:27>
base<0:3> 	::= instr<20:23>
offset<0:19> 	::= instr<0:19>

Instruction Execution 

LBI(::= fmt=9) --->
  IDU ---> Disp := SignExtend(offset)
  ODU ---> MAR := Reg[base]+Disp;
  OFU ---> Reg[dst.ld] := Mp[MAR];

Instruction Description

The 20 bit offset is sign extended. This is added to a base register and the result is used to fetch a word from memory that is placed into the register dst.ld.

11. Load Based + ALU2

010i dst.ld base dst/src src alu.2 8 bit offset

Instruction Format 

fmt<0:3> 	::= instr<28:31>
dst.ld<0:3> 	::= instr<24:27> 
base<0:3> 	::= instr<20:23> 
offset<0:7> 	::= instr<0:7> 
alu.2<0:3> 	::= instr<8:11> 
src<0:3> 	::= instr<12:15> 
dst/src<0:3> 	::= instr<16:19> 
i<0> 		::= instr<28>

Instruction Execution 

LBALU(::= fmt=4|fmt=5) --->
  IDU ---> Disp := SignExtend(offset);
  ODU ---> MAR := Reg[base] + Disp;
  SXU ---> (
	 i ---> Reg[dst/src] := OP2[alu.2](src,Reg[dst/src]); 
	~i ---> Reg[dst/src] := OP2[alu.2](Reg[src],Reg[dst/src]);
	 );
  OFU ---> Reg[dst.ld] := Mp[MAR];

Instruction Description

The 8 bit offset is sign extended. This is added to a base register and the result is passed to the MAR. The content of this memory location is then passed to the register indicated by dst.ld.

A list of all fields for alu.2 appears in appendix 1. The indicated ALU operation is performed during the execution phase of the instruction. The i field indicates whether the source field should be interpreted as a 4 bit literal or to indicate a register. The second operand is also the destination of the operation.

12. Load Base-Indexed+ ALU2

1101 dst.ld base dst/src src alu.2 000i index

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<4:7> 
dst.ld<0:3> 	::= instr<24:27> 
base<0:3> 	::= instr<20:23> 
index<0:3> 	::= instr<0:3> 
alu.2<0:3> 	::= instr<8:11> 
src<0:3> 	::= instr<12:15> 
dst/src<0:3> 	::= instr<16:19> 
i<0> 		::= instr<4>

Instruction Execution 

LIBALU(::= fmt=13 & (fmt2=0 | fmt2=1)) --->
  ODU ---> MAR := Reg[base] + Reg[index];
  SXU ---> (
 	 i ---> Reg[dst/src] := OP2[alu.2](src,Reg[dst/src]);
 	~i ---> Reg[dst/src] := OP2[alu.2](Reg[src],Reg[dst/src]);
  	);
  OFU ---> Reg[dst.ld] := Mp[MAR];

Instruction Description

The register pair indicated by base and index are added together and the result is passed to MAR. The content of this memory location are then passed to the indicated destination register.

A list of all fields for alu.2 appears in appendix 1. The indicated ALU operation is performed during the execution phase of the instruction. The i field indicates whether the source field should be interpreted as a 4 bit literal or to indicate a register. The second operand is also the destination of the operation.

13. Load Base-Shifted + ALU2

1101 dst.ld base dst/src src alu.2 010i shift

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<4:7> 
dst.ld<0:3> 	::= instr<24:27> 
base<0:3> 	::= instr<20:23> 
shift<0:3> 	::= instr<0:3> 
alu.2<0:3> 	::= instr<8:11> 
src<0:3> 	::= instr<12:15> 
dst/src<0:3> 	::= instr<16:19> 
i<0> 		::= instr<4>

Instruction Execution 

LSBALU(::= fmt=13 & (fmt2=4 | fmt2=5)) --->
  ODU ---> MAR := Reg[base] / 2**shift; { arithmetic }
  SXU ---> (
 	 i ---> Reg[dst/src] := OP2[alu.2](src,Reg[dst/src]);
 	~i ---> Reg[dst/src] := OP2[alu.2](Reg[src],Reg[dst/src]);
	 );
  OFU ---> Reg[dst.ld] := Mp[MAR];

Instruction Description

The register indicated by base is shifted right by the amount indicated in the shift field. The result is passed to the MAR. The content of the memory location indicated by MAR is passed to the register indicated by dst.ld.

A list of all fields for alu.2 appears in appendix 1. The indicated ALU operation is performed during the execution phase of the instruction. The i field indicates whether the source field should be interpreted as a 4 bit literal or to indicate a register. The second operand is also the destination of the operation.

14. Load Direct

1000 dst.ld 24 bit signed direct address

Instruction Format 

fmt<0:3> 		::= instr<28:31>
dst.ld<0:3> 		::= instr<24:27> 
DirectAddress<0:23> 	::= instr<0:23>

Instruction Execution 

LDL(:: fmt=8) --->
  IDU ---> Disp := SignExtend(DirectAddress);
  ODU ---> MAR := Disp;
  OFU ---> Reg[dst.ld] := Mp[MAR];

Instruction Description

The 24 bit address is sign extended. This is passed to the MAR. The content of the memory location indicated by MAR is passed to the register indicated by dst.ld.

15. Load Immediate

1100 dst.ld 24 bit signed immediate data

Instruction Format 

fmt<0:3> 		::= instr<28:31> 
dst.ld<0:3> 		::= instr<24:27> 
ImmediateData<0:23> 	::= instr<0:23>

Instruction Execution 

LDL(:: fmt=12) --->
  IDU ---> Disp := SignExtend(ImmediateData);
  ODU ---> Reg[dst.ld] := Disp;

Instruction Description

The 24 bit immediate data field is sign extended. This is passed to the register indicated by dst.ld.

16. LoadS Direct

1111 1000 24 bit signed address

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<24:27> 
Address<0:23> 	::= instr<0:23>

Instruction Execution 

LDS(:: fmt=15 & fmt2=8) --->
  IDU ---> Disp := SignExtend(Address);
  ODU ---> MAR := Disp;
  OFU ---> SUreg := Mp[MAR]

Instruction Description

The 24 bit address is sign extended and used to fetch a word from memory. This word is placed in the Surprise register SUreg.

17. SavePC

1111 1110 24 bit signed address

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<24:27> 
Address<0:23> 	::= instr<0:23>

Instruction Execution 

SAVEPC(:: fmt=15 & fmt2=14) ---> 
  IDU ---> Disp := SignExtend(Address);
  ODU ---> MAR := Disp;
  OFU ---> Mp[MAR] := PC(-3);

Instruction Description

The 24 bit address is sign extended. This is passed to the MAR. PC(-3) is subsequently stored in the memory location indicated by MAR.

18. Set Conditionally

1111 010i cond dst/src src all zero

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<24:27> 
cond<0:3> 	::= instr<20:23> 
dst<0:3> 	::= instr<16:19> 
src<0:3> 	::= instr<12:15> 
i<0> 		::= instr<24>

Instruction Execution 

SCND(::= fmt=15 & (fmt2=4 | fmt2=5)) --->
  SXU ---> (
  	~i -->  TEST[cond](Reg[src],Reg[dst/src]) ---> Reg[dst/src] := -1;
 	~i --> ~TEST[cond](Reg[src],Reg[dst/src]) ---> Reg[dst/src] := 0;
 	 i -->  TEST[cond](src,Reg[dst/src]) ---> Reg[dst/src] := -1;
 	 i --> ~TEST[cond](src,Reg[dst/src]) ---> Reg[dst/src] := 0;
	 );

Instruction Description

The operands indicated by src and dst are compared on the basis of test indicated by the cond field. If the result of that test is true then the register indicated by dst is set to all ones, otherwise it is set to zero. The i field indicates whether src is to be interpreted as a literal or as indication of the register to be used.

19. Store Based

1011 src.st base 20 bit signed offset

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
src.st<0:3> 	::= instr<24:27> 
base<0:3> 	::= instr<20:23> 
offset<0:19> 	::= instr<0:19>

Instruction Execution 

SBI(::= fmt=11) --->
  IDU ---> Disp := SignExtend(offset)
  ODU ---> MAR := Reg[base]+Disp;
  SXU ---> Mp[MAR] := Reg[src.st];

Instruction Description

The 20 bit offset is sign extended. This is added to the register indicated by base. The result is passed to the MAR. The content of the register indicated by src.st is then stored into the memory location indicated by MAR.

20. Store Based + ALU2

011i src.st base dst/src src alu.2 8 bit offset

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
src.st<0:3> 	::= instr<24:27> 
base<0:3> 	::= instr<20:23> 
offset<0:7> 	::= instr<0:7> 
alu.2<0:3> 	::= instr<8:11> 
src<0:3> 	::= instr<12:15> 
dst/src<0:3> 	::= instr<16:19> 
i<0> 		::= instr<28>

Instruction Execution 

SBALU(::= fmt=6 | fmt=7) --->
 IDU ---> Disp := SignExtend(offset);
 ODU ---> MAR := Reg[base] + Disp;
 SXU ---> (
	 Mp[MAR] := Reg[src.st]
	 i ---> Reg[dst/src] := OP2[alu.2](src,Reg[dst/src]);
	~i ---> Reg[dst/src] := OP2[alu.2](Reg[src],Reg[dst/src]);
	 );

Instruction Description

The 8 bit offset is sign extended. This is added to a base register and the result is passed to the MAR. The content of the register indicated by src.st is then stored into the memory location indicated by MAR.

A list of all fields for alu.2 appears in appendix 1. The indicated ALU operation is performed during the execution phase of the instruction. The i field indicates whether the source field should be interpreted as a 4 bit literal or to indicate a register. The second operand is also the destination of the operation. Reg[src.st] and Reg[dst/src] have to be different i.e. no bypassing takes place.

21. Store Base-Indexed+ ALU2

1101 src.st base dst/src src alu.2 001i index

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<4:7> 
src.st<0:3> 	::= instr<24:27> 
base<0:3> 	::= instr<20:23> 
index<0:3> 	::= instr<0:3> 
alu.2<0:3> 	::= instr<8:11> 
src<0:3> 	::= instr<12:15> 
dst/src<0:3> 	::= instr<16:19> 
i<0> 		::= instr<4>

Instruction Execution 

SIBALU(::= fmt=13 & (fmt2=2 | fmt2=3)) --->
  ODU ---> MAR := Reg[base] + Reg[index];
  SXU ---> (
	 Mp[MAR] := Reg[src.st]
	 i ---> Reg[dst/src] := OP2[alu.2](src,Reg[dst/src]);
 	~i ---> Reg[dst/src] := OP2[alu.2](Reg[src],Reg[dst/src]);
	 );

Instruction Description

The register pair indicated by base and index are added together and the result is passed to MAR. The content of the register indicated by src.st is then stored into the memory location referenced by MAR.

A list of all fields for alu.2 appears in appendix 1. The indicated ALU operation is performed during the execution phase of the instruction. The i field indicates whether the source field should be interpreted as a 4 bit literal or to indicate a register. The second operand is also the destination of the operation. Reg[src.st] and Reg[dst/src] have to be different i.e. no bypassing takes place.

22. Store Base-Shifted+ ALU2

1101 src.st base dst/src src alu.2 011i shift

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<4:7> 
src.st<0:3> 	::= instr<24:27> 
base<0:3> 	::= instr<20:23> 
shift<0:3> 	::= instr<0:3> 
alu.2<0:3> 	::= instr<8:11> 
src<0:3> 	::= instr<12:15> 
dst/src<0:3> 	::= instr<16:19> 
i<0> 		::= instr<4>

Instruction Execution 

SSBALU(::= fmt=13 & (fmt2=6 | fmt2=7)) --->
  ODU ---> MAR := Reg[base] / 2**shift; { arithmetic }
  SXU ---> (
	 Mp[MAR] := Reg[src.st]
	 i ---> Reg[dst/src] := OP2[alu.2](src,Reg[dst/src]);
	~i ---> Reg[dst/src] := OP2[alu.2](Reg[src],Reg[dst/src]);
 	 );

Instruction Description

The register indicated by base is shifted right by the amount indicated in the shift field. The result is passed to the MAR. The content of the register indicated by src.st is then stored into the memory location referenced by MAR.

A list of all fields for alu.2 appears in appendix 1. The indicated ALU operation is performed during the execution phase of the instruction. The i field indicates whether the source field should be interpreted as a 4 bit literal or to indicate a register. The second operand is also the destination of the operation. Reg[src.st] and Reg[dst/src] have to be different i.e. no bypassing takes place.

23. Store Direct

1010 src.st 24 bit signed address

Instruction Format 

fmt<0:3> 		::= instr<28:31> 
src.st<0:3> 		::= instr<24:27> 
DirectAddress<0:23> 	::= instr<0:23>

Instruction Execution 

STD(:: fmt=10) --->
  IDU ---> Disp := SignExtend(DirectAddress);
  ODU ---> MAR := Disp;
  SXU ---> Mp[MAR] := Reg[src.st];

Instruction Description

The 24 bit address is sign extended. This is passed to the MAR. The content of the register indicated by src.st is then stored into the memory location indicated by MAR.

24. StorePC Based

1110 1011 base 20 bit signed offset

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<24:27> 
base<0:3> 	::= instr<20:23> 
offset<0:19> 	::= instr<0:19>

Instruction Execution 

SPCB(::= fmt=14 & fmt2=11) --->
  IDU ---> Disp := SignExtend(offset)
  ODU ---> MAR := Reg[base]+Disp;
  SXU ---> Mp[MAR] := PC(current)+1;

Instruction Description

The 20 bit offset is sign extended. This is added to the register indicated by base. The result is passed to the MAR. The contents of the current program counter PC are then stored into the memory location indicated by MAR. Note that the PC has been incremented twice since this instruction was fetched.

25. StorePC Based + ALU2

1110 011i base dst/src src alu.2 8 bit offset

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<24:27> 
base<0:3> 	::= instr<20:23> 
offset<0:7> 	::= instr<0:7> 
alu.2<0:3> 	::= instr<8:11> 
src<0:3> 	::= instr<12:15> 
dst/src<0:3> 	::= instr<16:19> 
i<0> 		::= instr<24>

Instruction Execution 

SPCALU(::= fmt=14 & (fmt2=6 | fmt2=7)) --->
  IDU ---> Disp := SignExtend(offset);
  ODU ---> MAR := Reg[base] + Disp;
  SXU ---> (
 	 Mp[MAR] := PC(current)+1;
	 i ---> Reg[dst/src] := OP2[alu.2](src,Reg[dst/src]);
	~i ---> Reg[dst/src] := OP2[alu.2](Reg[src],Reg[dst/src]);
	 );

Instruction Description

The 8 bit offset is sign extended. This is added to a base register and the result is passed to the MAR. The contents of the current program counter PC are then stored into the memory location indicated by MAR. Note that the PC has been incremented twice since this instruction was fetched.

A list of all fields for alu.2 appears in appendix 1. The indicated ALU operation is performed during the execution phase of the instruction. The i field indicates whether the source field should be interpreted as a 4 bit literal or to indicate a register. The second operand is also the destination of the operation. Reg[src.st] and Reg[dst/src] have to be different i.e. no bypassing takes place.

26. StorePC Direct

1110 1010 24 bit signed address

Instruction Format 

fmt<0:3> 	::= instr<28:31> 
fmt2<0:3> 	::= instr<24:27> 
Offset<0:23> 	::= instr<0:23>

Instruction Execution 

SPC(:: fmt=14 & fmt2=10) --->
  IDU ---> Disp := SignExtend(Offset);
  ODU ---> MAR := Disp;
  SXU ---> Mp[MAR] := PC(current)+1;

Instruction Description

The 24 bit address is sign extended. This is passed to the MAR. The contents of the current program counter PC are then stored into the memory location indicated by MAR. Note that the PC has been incremented twice since this instruction was fetched. Note that the PC has been incremented twice since this instruction was fetched.

27. StoreSU Direct

1111 1001 24 bit signed address

Instruction Format 

fmt<0:3> ::= instr<28:31> 
fmt2<0:3> ::= instr<24:27> 
Address<0:23> ::= instr<0:23>

Instruction Execution 

STS(:: fmt=15 & fmt2=9) --->
  IDU ---> Disp := SignExtend(Address);
  ODU ---> MAR := Disp;
  SXU ---> Mp[MAR] := SUreg;

Instruction Description

The 24 bit address is sign extended. This is passed to the MAR. The Surprise register SUreg is subsequently stored in the memory location indicated by MAR.

28. Trap Conditionally

1111 001i cond src2 src1 11 bit signed code  

Instruction Format 

fmt<0:3> ::= instr<28:31>
fmt2<0:3> ::= instr<24:27> 
cond<0:3> ::= instr<20:23> 
src2<0:3> ::= instr<16:19> 
src1<0:3> ::= instr<12:15> 
Code<0:11> ::= instr<1:11> 
i<0> ::= instr<24>

Instruction Execution 

TRAP(::= fmt=15 & (fmt2=2 | fmt2=3)) --->
  IDU ---> Disp := SignExtend(Code);
  ODU ---> SUreg := Disp;
  SXU ---> (
 	~i ---> TEST[cond](Reg[src1],Reg[src2]) ---> PC(current) :=0;
 	 i ---> TEST[cond](src1,Reg[src2]) ---> PC(current) :=0;
 	 );

Instruction Description

The 11 bit trap vector in instr<1:11> is sign extended and written into bits 1 to 12 of the Surprise register SUreg. Bit 0 is ignored. The condition indicated by cond is tested on the operands indicated by src1 and src2. The i field indicates whether src1 is to be interpreted as a literal or as the register to be used as the first argument of the test. If the test is true then control is transferred to location 0.In this case the instruction which follows the trap instruction sequentially will not be executed. PC(-3) will point to the following instruction.

Appendix I

ALU Operations

Opcodes

Mnemonic: mov
Opcode: 0000
Operation: register move
Notes: The source operand of a three operand immediate mov instruction is the 8-bit signed byte formed by concatenating the two source fields. The second source operand of a three operand register mov instruction is ignored. For consistency with other ALU operations, this register should be the same as the destination register.
Mnemonic: add
Opcode: 0001
Operation: addition
Notes:  
Mnemonic: sub
Opcode: 0010
Operation: subtraction
Notes: sub src1,src2 is defined as result:=src2-src1
Mnemonic: subr
Opcode: 0011
Operation: reverse subtraction
Notes: The three operand register subr is redundant. Immediate subr yields negation: subr #0,ra is equivalent to neg r1 and subr #0,r1,r2 is equivalent to movneg r1,r2
Mnemonic: and
Opcode: 0100
Operation: bitwise and
Notes:  
Mnemonic: or
Opcode: 0101
Operation: bitwise inclusive or
Notes:  
Mnemonic: xor
Opcode: 0110
Operation: bitwise exclusive or
Notes: When true and false are represented by 1 and 0, xor #1,r1 provides Boolean negation.
Mnemonic: rlc
Opcode: 0111
Operation: combined shift left
Notes: Combined shift left is used in field extraction and insertion. The 5 low order bits Lo register specify the shiftcount, sc. Bits 31..0 of the destination register will contain bits (31 -sc)..0 of source2 || bits 31..(31-(sc-1)) of source1.
Mnemonic: sll
Opcode: 1000
Operation: logical shift left
Notes: Immediate shift count only. The shift count is encoded in the 4-bit first source operand field; the high order bit of the shift amount is stored in the immediate bit. (For a variable shift, the shift count must first be loaded into LO, then an implicit source ALU instruction executed.)
Mnemonic: srl
Opcode: 1001
Operation: logical shift right
Notes: Immediate shift count only. The shift count is encoded in the 4-bit first source operand field; the high order bit of the shift amount is stored in the immediate bit. (For a variable shift, the shift count must first be loaded into LO, then an implicit source ALU instruction executed.)
Mnemonic: sra
Opcode: 1010
Operation: arithmetic shift right
Notes: Immediate shift count only. The shift count is encoded in the 4-bit first source operand field; the high order bit of the shift amount is stored in the immediate bit. (For a variable shift, the shift count must first be loaded into LO, then an implicit source ALU instruction executed.)
Mnemonic: rol
Opcode: 1011
Operation: rotate left
Notes: Immediate shift count only. The shift count is encoded in the 4-bit first source operand field; the high order bit of the shift amount is stored in the immediate bit. (For a variable shift, the shift count must first be loaded into LO, then an implicit source ALU instruction executed.)
Mnemonic: xc
Opcode: 1100
Operation: extract character
Notes: The two low order bit of src1 determine which byte is extracted from src2. This byte is placed in the low order byte of the destination register. The three high order bytes of the destination are set to all 0.
Mnemonic: ic
Opcode: 1101
Operation: insert character
Notes: The low order byte of the first source is inserted into the destination. The two low order bit of the Lo register determine which byte is overwritten. All other fields of the destination remain unchanged. The second source is always ignored.
Mnemonic:  
Opcode: 1110
Operation: implicit source
Notes: The first source operand field provides the next 4 opcode bits. The immediate bits i' and i are ignored.
Mnemonic:  
Opcode: 1111
Operation: implicit destination
Notes: The src/dst or dst operand field provides the next 4 opcode bits. The immediate bits i' and i are used as usual.

Implicit Source

(alu.2=14) or (alu.3=14) The opcode for the following operations is stored in src (for alu.2) or in src1 (for alu.3).

Mnemonic Opcode Operation Notes
  0000 reserved Privileged
  0001 reserved Privileged
mov Ap,dst 0010 move Aphid to register Privileged
mov Ma,dst 0011 move MA to register Privileged
mov Hi,dst 0100 move Hi to register Non Privileged
mov Lo,dst 0101 move Lo to register Non Privileged
  0110 reserved Non Privileged
mov PC,dst 0111 move PC to register Non Privileged
sll Lo,dst 1000 variable sll Non Privileged
srl Lo,dst 1001 variable srl Non Privileged
sra Lo,dst 1010 variable sra Non Privileged
rol Lo,dst 1011 variable rol Non Privileged
not operand 1100 bitwise not Non Privileged

Implicit Destination

(alu.2=15) or (alu.3=15) The opcode for these operations is placed in the dst/src field (for alu.2) or in the dst field (for alu.3)

Mnemonic Opcode Operation Notes
  0000 reserved Privileged
  0001 reserved Privileged
mov src,Ap 0010 Load Aphid Privileged
mov src,Ma 0011 Load MA Privileged
mov src,Hi 0100 Load Hi Non Privileged
mov src,Lo 0101 Load Lo Non Privileged
  0110 reserved Non Privileged
mov src,PC 0111 Load PC Non Privileged
msetup src,Hi 1000 Multiply set up Non Privileged
mstep src,Hi 1001 Multiply step signed Non Privileged
umend src,Hi 1010 Unsigned mult. step Non Privileged
dstep src,Hi 1011 Signed divide step Non Privileged

Appendix II

Integer Multiplication and Division

This section is summary of the specials features incorporated in MIPS to speed up multiplication and division. First we describe the special registers and multiply/divide step ALU pieces. Then we illustrate their use and give some typical examples.

Figure II-1: Register use for multiplication

Three special registers are needed for multiplication and division (See figure II-1 and figure II-2; the arrows indicate shift operations). The Hi register (High order) contains the high order bits of the dividend during division and the high order bits of the accumulating product during multiplication. The Lo register (Low order) contains the low order bits of the dividend and accumulates the quotient during division. During multiplication it contains the low order bits of the product. It also feeds the multiplier to the Booth PLA through bits Lo0 and Lo1. The Db register contains a single bit from the last step of the two bit Booth algorithm during multiplication and is not used during division.

Four special instructions are provided for multiplication and division: MSetUp, MStep, UMEnd, and DStep. These instructions use implicit operands in the Hi, Lo, and Db registers must be loaded with move instructions.

Figure II-2: Register use for division

II.1. Multiplication

Both signed and unsigned multiplication are supported. In unsigned multiplication, the multiplicand and the multiplier are considered to be 32 bit positive quantities. Otherwise, in signed implementations, they are interpreted as signed entities in two's complement.

For multiplications, both Hi and Db registers must be cleared, then the multiplier is loaded into the Lo register. The multiplicant can be in any general purpose register Ri.

MSetUp Prepare for multiply sequence. This instruction cleares the Db register and does the first multiply step. This step is functionally equivalent to executing a MStep which is described below.
MStep Two bit Booth multiply step using Hi, Lo, Db, and multiplicand in Rn. Each multiply step reads the Hi register and adds it to 0, -1, -2, 1, or 2 times the multiplicand (in Rn) depending on bits 1 and 0 of the Lo register and bit 0 of the Db register. (See Booth table in figure II-3). The result of this operation can be as large as three times the largest 32 bit signed number: hence 34 bits are required to hold the result. (I.e. in 4x4 bit multiplication, 0111 x 0011 = 010101) This necessitates a 34 bit adder with sign extension on each input. Note that if a 32 bit input is multiplied by two, its sign extension into bits 33 and 32 remains the same whether shifted or not. These two extra bits can also be used to detect overflow in normal addition with sign extended inputs: overflow has occured if bits 32 and 31 are not the same.

The 34 bit result must be writen into Hi<31:0>Lo<31:30>. While the Hi register is being read and written in MStep, the Lo register must be shifted right two bits (to make room for the extra two bits of the 34 bit result). This also shifts the multiplier in the low order bits of the Lo register into proper position for examination in the next multiply step. During this shift Lo0 gets shifted into Db0. A sequence of MSteps generates a 64 bit product in the Hi-Lo register pair. All 64 bits are available through move instructions. If single precision arithmetic is used, anything but the sign extension of the 32 bit qualtity from Lo in Hi will indicate overflow. This condition can be checked for in software if desired. Arithmetic overflow on particular MStep is not possible once 34 bits are provided for each result.

UMEnd Unsigned multiplication end using Hi, Lo, Db, and multiplicand in Rn. If ythe numbers are unsigned, UMEnd executed after 16 MSteps provides unsigned multiplication. UMEnd adds the multiplicand (from register Rn) once to Hi if Db = 1. If Db = 0, Hi is left unchanged (see figure II-4). The result is written straight into Hi<31:0> unlike in MStep where shifting of Hi and Lo takes place. Arithmetic overflow is not possible in a UMEnd.

 

Lo1 Lo0 Db0 Action
0 0 0 Shift only
0 0 1 Add 1x and Shift
0 1 0 Add 1x and Shift
0 1 1 Add 2x and Shift
1 0 0 Substract 2x and Shift
1 0 1 Substract 1x and Shift
1 1 0 Substract 1x and Shift
1 1 1 Shift only

Figure II-3: Booth PLA for MPStep

Lo1 Lo0 Db0 Action
x x 0 Nothing
x x 1 Add 1x

Figure II-4: Booth PLA for UMEnd

II.2. Multiplication examples

We give here examples how multiplication can be implemented using those step instructions. Of course, many equivalent versions are acceptable, i.e. the sequence of 15 MStep instructions can be organized in a loop.

Sample code sequence for multiply: Sixteen two bit Booth multiply step instructions must be executed for a 32x32 bit signed multiply. These can be packed into 8 instructions, but we give here the unpacked version:

			; Signed multiplication
			; Rtemp is a temporary GP register
			; Rmultiplier contains the multiplier
			; Rmultiplicand contaains the multiplicand
			; Rproduct := Rmultiplier * Rmultiplicand
mov #0, Hi 		; Clear Hi
mov Rmultiplier, Lo 	; Move multiplier to Lo
msetup Rmultiplicand 	; Clear Db, first multiply step
mstep Rmultiplicand 	; 15 msteps compute 2 bits each
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
			; Test for overflow
mov Lo, Rproduct 	; Retreive low order bits of product
mov Hi, Rtemp 		; Retreive high order bits of product
sra #31, Rproduct 	; Sign extend low order bits of product
xor Rproduct, Rtemp 	; All bits of Rtemp will be 0 iff Rtemp contains
			; only the sign extension of the low order bits
mov Lo, Rproduct 	; Retreive product
tno #0, Rtemp, overflow ; Trap if Hi differs from the sign extension

With instruction packing, 13 instructions can implement a 32x32 bit signed integer multiply with trap on overflow of the 32 bit result. Without trap on overflow, only 10 instructions are needed resulting 32x32 bit multiplication in 5µs for an 8MHz MIPS.

Sample code for unsigned multiply: For a 32x32 bit unsigned multiplication sixteen multiply steps are needed; they are followed by one UMEnd step. 

			; Unsigned multiplication
			; Rtemp is a temporary GP register
			; Rmultiplier contains the multiplier
			; Rmultiplicand contaains the multiplicand
			; Rproduct := Rmultiplier * Rmultiplicand
mov #0, Hi 		; Clear Hi
mov Rmultiplier, Lo 	; Move multiplier to Lo
msetup Rmultiplicand 	; Clear Db, first multiply step
mstep Rmultiplicand 	; 15 msteps compute 2 bits each
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
mstep Rmultiplicand
umend Rmultiplicand
mov Lo, Rproduct 	; Retreive product
			; test for overflow

With instruction packing, 13 instructions can implement a 32x32 bit unsigned integer multiply with trap on overflow of the 32 bit product. Without trap on overflow, only 10 instructions are required.

II.3. Division

For divisions and remainder operations, only the Hi and Lo register are used. A 64 bit positive number, the divident, is loaded into the Hi-Lo register pair, the Db register is not used. The divisor can be any general purpose register Rn.

DStep Positive divide step using Hi, Lo, and divisor in Rn. Divide step implements non restoring division by either adding or substracting the divisor (in Rn) form the dividend (in Hi). The decision to add or substract is based on the sign of Hi.

Both the divisor and dividend must be positive to start. A positive 64 bit dividend must be loaded into the Hi-Lo register pair. If the dividend is not 64 bits, it must be loaded into Lo, and Hi mus be loaded with zero. DStep reads Hi<30:0>Lo31 and adds Rn if Hi31 = 1 or substracts Rn if Hi31 = 0. The result is stored in Hi. While this read shifted and write to Hi occurs, Lo also shifts one bit left. The quotient bit generated is the complement of the new Hi31 and is inserted into Lo0 after the left shift by one takes place. After division is complete, a positive quotient is left in Lo. The quotient in Lo may need to be negated (via conventional operations in a general register) to match its expected sign based on the signs of the dividend and divisor.

If the remainder is desired and it is negative, it must be restored by addition of the divisor. Then it must be negated if the original dividend was negative.

Overflow is not possible in 32/32 bit division. In 64/32 bit division overflow occurs if Hi31 <> Hi30 as the read shifted left is done in DStep. no unsigned division is supported. Implementing unsigned division requires expansion of the Hi and Lo registers to 33 bits. Adding one more to these registerss is much more revolting than a 34 bit ALU because saving each of these registers would require two 32 bit stores in a simple scheme. In a more sophisticated scheme, the extra two bits could be put in Db register, since only one bit of it si used. However the wiring for this scheme would be extremly irregular.

II.4. Division and remainder examples

These examples give an idea on how a divide sequence can be implemented. Again, various trade-offs are possible, i.e. loops can be unrolled.

Sample code for signed divide: 

			; Divide sequence
			; Rdividend contains the dividend
			; Rdivisor holds the divisor
			; Rquotient := Rdividend / Rdivisor
			; Rtemp1 and Rtemp2 are temporary GP registers
teq #0, Rdivisor, zerodivide ; Trap on zero divide
			; The next 3 instructions compute
			; Rtemp2 := abs(dividend)
sra #31, Rdividend, Rtemp1
xor Rtemp1, Rdividend, Rtemp2
sub Rtemp1, Rtemp2
mov Rtemp2, Lo 		; Move abs(dividend) to Lo
			; The next 3 instructions compute
			; Rtemp2 := abs(divisor)
sra #31, Rdivisor, Rtemp1
xor Rtemp1, Rdivisor, Rtemp2
sub Rtemp1, Rtemp2
mov #0, Hi 		; Clear Hi
mov #0, Rtemp1 		; Use Rtemp1 as loop counter
			; 32 division steps compute the quotient in Lo
			; each iteration includes 4 dsteps
LOOP:
dstep Rtemp2
dstep Rtemp2
dstep Rtemp2
dstep Rtemp2
add #1, Rtemp1
bgt #8, Rtemp1, LOOP 	; If Rtemp1 < 8 then continue
			; Lo = abs(quotient), check if sign
			; adjustment needed
xor Rdivisor, Rdividend, Rtemp1
sra #31, Rtemp1 	; Rtemp1 = 0 if sign of quotient correct, Rtemp1=-1
			; if negation is required
mov Lo, Rquotient 	; Retreive abs(quotient)
			; Adjust sign
xor Rtemp1, Rquotient 	; Rquotient=quotient (if Rtemp1 = 0) otherwise
			; Rquotient = quotient-1 (if Rtemp = -1)
sub Rtemp1, Rquotient 	; Add 1 (sub -1) if quotient needs adjustment
			; otherwise, substract 0

With packing, 13 instructions are needed to implement signed division with trap on division by zero. No other overflow conditions are possible for 32/32 bit division. The particular code sequence given trades execution time for reduced instruction space by looping four times over divide steps. The code can be sped up approx. 30% by completely unrolling in DStep loop, but this increases the instruction count from 13 words to 24 words. Thus division on an 8MHz MIPS takes 16.5µs for the loop version and 21µs for the straight line version.

Sample code sequence for signed remainder: The same instructions as for divide setup and divide loop are needed as above. Then, the reminder of abs(dividend/divisor) is retreived. If it is negative, it is restored. To get a properly signed remainder, we determine the sign of the dividend and adjust the sign of the remainder accordingly. This means signed remainder takes 15 instructions/17.5µs (loop version) or 26 instructions/13µs (straight line) on an 8MHz MIPS. 

			; Code sequence for remainder
			; Rdividend contains the dividend
			; Rdivisor holds the divisor
			; Rquotient := remainder of Rdividend / Rdivisor
			; Rtemp1 and Rtemp2 are temporary GP registers
teq #0, Rdivisor, zerodivide ; Trap on zero divide
			; The next 3 instructions compute
			; Rtemp2 := abs(dividend)
sra #31, Rdividend, Rtemp1
xor Rtemp1, Rdividend, Rtemp2
sub Rtemp1, Rtemp2
mov Rtemp2, Lo 		; Move abs(dividend) to Lo
			; The next 3 instructions compute
			; Rtemp2 := abs(divisor)
sra #31, Rdivisor, Rtemp1
xor Rtemp1, Rdivisor, Rtemp2
sub Rtemp1, Rtemp2
mov #0, Hi 		; Clear Hi
mov #0, Rtemp1 		; Use Rtemp1 as loop counter
			; 32 division steps compute the quotient in Lo
			; each iteration includes 4 dsteps
LOOP:
dstep Rtemp2
dstep Rtemp2
dstep Rtemp2
dstep Rtemp2
add #1, Rtemp1
bgt #8, Rtemp1, LOOP 	; If Rtemp1 < 8 then continue
			; Hi = remainder, restore if negative
mov #1, Rtemp1
sra #31, Hi 		; Sign extend the remainder
and Rtemp1, Rtemp2 	; Rtemp2 = 0 if Hi >= 0, Rtemp2 = divisor
			; if Hi < 0
mov Hi, Rtemp1 		; Retreive the remainder
add Rtemp1, Rtemp2 	; Add divisor or 0
			; The remainder has now been restored.
			; Negate if dividend < 0
sra #31, Rdividend, Rtemp1 ; Rtemp1 contains sign extension of dividend
and Rtemp2, Rtemp1 	; Rtemp1 = 0 is sign correct, else Rtemp1=remainder
			; if sign correct, Rremainder := remainder - 0 - 0
			; otherwise, Rremainder := remainder - 2*remainder
sub Rtemp1, Rtemp2, Rremainder
sub Rtemp1, Rremainder

Appendix III Conditions

Suffix Encoding Condition Notes
lt 0000 less than src1 < src2 (signed)
ge 0001 greater than or equal src1 >= src2 (signed)
le 0010 less than or equal src1 <= src2 (signed)
gt 0011 greater than src1 > src2 (signed)
lo 0100 lower than src1 < src2 (unsigned)
hs 0101 higher than or same src1 >= src2 (unsigned)
ls 0110 lower than or same src1 <= src2 (unsigned)
hi 0111 higher than src1 > src2 (unsigned)
zand 1000 and is zero bitwise and(src1,src2)=0
nzand 1001 and is not zero bitwise and(src1,src2)<>0
zor 1010 or is zero bitwise or(src1,src2)=0
nzor 1011 or is nonzero bitwise or(src1,src2)<>0
eq 1100 equal src1=src2
ne 1101 not equal src1<>src2
  1110   reserved
  1111   reserved

 

Appendix IV Cross Reference

Group A: instr<28:31>
instr<28:31> Instruction Notes
0000    
0001    
0010    
0011 ALU3 + ALU2 See Appendix I for the decoding of the ALU operation
0100    
0101 Load Based + ALU2  
0110    
0111 Store Based + ALU2  
1000 Load Direct  
1001 Load Based  
1010 Store Direct  
1011 Store Based  
1100 Load Immediate  
1101 Group B  
1110 Group C  
1111 Group D  

 

Group B: instr<28:31> + instr<4:7>
instr<28:31> instr<4:7> Instruction
1101 0000  
1101 0001 Load Base-Indexed + ALU2
1101 0010  
1101 0011 Store Base-Indexed + ALU2
1101 0100  
1101 0101 Load Base-Shifted + ALU2
1101 0110  
1101 0111 Store Base-Shifted + ALU2

 

Group C: instr<28:31> + instr<24:27>
instr<28:31> instr<24:27> Instruction
1110 0100  
1110 0101 Jump Based Indirect + ALU2
1110 0110  
1110 0111 Store PC Based + ALU2
1110 1000 Jump Indirect
1110 1001 Jump Based Indirect
1110 1010 StorePC Direct
1110 1011 StorePC Based
1110 1100 Jump Direct
1110 1101 Jump Based
1110 1110 Branch Unconditionally

 

Group D: instr<28:31> + instr<24:27>
instr<28:31> instr<24:27> Instruction
1111 0000  
1111 0001 Branch Conditionally
1111 0010  
1111 0011 Trap Conditionally
1111 0100  
1111 0101 Set Conditionally
1111 1000 LoadS Direct
1111 1001 StoreSU Direct
1111 1110 SavePC
1111 1111 Jump Indirect and Setup S-register